esunit1.pptx

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EMBEDDED
SYSTEMS

UNIT – 1
PART-A
1. Embedded Systems – Introduction (Definition, Applications and Classification)
2. Features and architecture considerations(ROM,RAM,TIMERS…)
3. RISC Vs. CISC
4. Von-Neumann & Harvard Architecture
5. Memory mapped I/O and Isolated I/O
6. Little-Endian and Big-Endian
PART-B
1. Low Power RISC- MSP 430 : Introduction & Variants of MSP 430 family
2. MSP430F2013 - Block diagram & features
3. Memory map of MSP430
4. MSP430 –CPU architecture & registers
5. Addressing modes of MSP430
6. Instruction formats & Instruction Timings of MSP430
7. Instruction set of MSP430
8. Sample Embedded system on MSP430

INTRODUCTION TO EMBEDDED SYSTEMS
• Definition :An embedded system is an electronic/electro-
mechanical system designed to perform a specific function and is
combination of both hardware and firmware (software). The program
instructions written for embedded systems are referred to as firmware,
and are stored in Read-Only-Memory or Flash memory.

Purpose of Embedded System
• Data Collection/Storage/Representation
• Data communication
• Data processing
• Monitoring
• Control
• Application specific user interface

• Applications of Embedded Systems
• Household appliances
• Automotive industry
• Home automation & security systems
• Telecom
• Computer peripherals
• Computer networking systems
• Healthcare
• Banking & Retail
• Card Readers
• Measurements & Instrumentation
• Missiles and Satellites
• Robotics
• Motor control systems
• Entertainment systems
• Signal & Image processing
Medical
Automotive
Communications
Comsumer Industrial
Military

• Classification of Embedded Systems:
• The classification of embedded system is based on
following criteria's:
• On generation
• On complexity & performance

• Classification based on generation
• 1. First generation(1G):8-bit μp and 4-bit μc.
• 2. Second generation(2G):16-bit μp and 8-bit μc.
• 3. Third generation(3G):32-bit μp & 16-bit μc.
• 4. Fourth generation(4G):64-bit μp & 32-bit μc.

• Classification based on Complexity and
performance
1. Small-scale
• Simple applications where the performance requirements are not time-critical.
• Built around low performance and low cost 8 or 16 bit μp/μc.
2. Medium-scale
• Slightly complex in hardware and firmware requirement.
• Built around medium performance and low cost 16 or 32 bit μp/μc.
3. Large-scale
• Highly complex hardware & firmware.
• Built around 32 or 64 bit RISC μp/μc or PLDs or SoC or multi-core processors.

Features and architecture considerations
• Basic elements of an embedded system:

• System core:-Central processing unit
This include:
• Arithmetic logic unit (ALU), which performs
computation.
• Registers needed for the basic operation of the
CPU, such as the program counter (PC), stack
pointer (SP), and status register (SR).
• Further registers to hold temporary results.
• Instruction decoder and other logic to control the
CPU, handle resets, and interrupts, and so on.

• Memory for the program: Non-volatile (read-only
memory, ROM), meaning that it retains its contents
when power is removed.
• Memory for data: Known as random-access memory
(RAM) and usually volatile.
• Input and output ports: To provide digital
communication with the outside world.
• Address and data buses: To link these subsystems to
transfer data and instructions.
• Clock: To keep the whole system synchronized. It may
be generated internally or obtained from a crystal or
external source; modern MCUs offer considerable
choice of clocks.

Common peripherals:-
• Timers: Most microcontrollers have at least one
timer because of the wide range of functions that
they provide.
• They provide a regular “tick” that can be used to
schedule tasks in a program. Many programs are
awakened periodically by the timer to perform
some action—measure the temperature and
transmit it to a base station, for example—then go
to sleep (enter a low-power mode) until awakened
again. This conserves power, which is vital in
battery-powered applications.

• Watchdog timer: This is a safety feature, which
resets the processor if the program becomes stuck
in an inﬁnite loop.
• Communication interfaces: A wide choice of
interfaces is available to exchange information with
another IC or system. They include serial peripheral
interface (SPI), inter-integrated circuit (I²C or IIC),
asynchronous (such as RS-232), universal serial bus
(USB), controller area network (CAN), ethernet, and
many others.

• Non-volatile memory for data: This is used to store
data whose value must be retained when power is
removed. Serial numbers for identiﬁcation and
network addresses are two obvious candidates.
• Analog-to-digital converter: This is very common
because so many quantities in the real world vary
continuously.

• Digital-to-analog converter: This is much less
common, because most analog outputs can be
simulated using PWM. An important exception used
to be sound, but even here, the use of PWM is
growing in what are called class D ampliﬁers.
• Real-time clock: These are needed in applications
that must track the time of day. Clocks are obvious
examples but data loggers are also an important
case.

• Monitor, background debugger, and embedded
emulator: These are used to download the program
into the MCU and communicate with a desktop
computer during development.
• The processor communicates with these peripherals by
reading from, and writing to, particular addresses in
memory. These memory locations are called special
function registers or peripheral registers to distinguish
them from ordinary memories, which simply store
data, but exactly the same commands are used—no
special commands are needed. In practice,
microcontrollers spend much of their time handling the
peripheral registers.

• RISC Vs CISC :
RISC (Reduced Instruction Set Computer)) CISC (Complex Instruction Set Computer)
Supports lesser number of instructions. Supports greater number of instructions.
Supports few addressing modes for memory access and data transfer
instructions.
Supports many addressing modes for memory access and data transfer
instructions.
Single, fixed length instructions Variable length instructions
Instructions take fixed amounts of time for execution Instructions take varying amounts of time for execution
Instruction pipelining works effectively and increases the execution
speed.
Instruction pipelining concept is not effectively works as different sizes and
different execution times of instructions.
Orthogonal instruction set (allows each instruction to operate on any
register and use any addressing mode.)
Non-orthogonal set (all instructions are not allowed to operate on any
register and use any addressing mode.
Less silicon usage and decoding logic is not complex.
More silicon usage since more additional decoder logic is required to
implement the complex instruction decoding.
Because of the simple instructions, the design of compiler is easy.
Because of large amount of different and complex instructions, the design
of compiler is complex.
A larger number of registers are available. Limited no. of general purpose registers

• HARVARD ARCHITECTURE Vs VON-NEUMANN ARCHITECTURE :
It has separate buses for instruction as
well as data fetching. This means that,
the data memory and program memory
are separated.
It shares single common bus for instruction
and data fetching. This means that only one
set of addresses covers both data memory
and program memory. The memory map
shows the addresses at which each type of
memory is located.

Easier to pipeline, so high performance can be achieve.
Low performance as compared to Harvard
architecture
It allows simultaneous access to the program and data memories. For instance, the CPU
can read an operand from the data memory at the same time as it reads the next
instruction from the program memory.
First fetches the instruction and then fetches the data. The two separate fetches
slows down the controller’s operation.
Because several memory cycles are needed to extract a full instruction from
memory, this architecture is intrinsically less efficient.
Since data memory and program memory are stored physically in different locations, no
chances exist for accidental corruption of program memory
Accidental corruption of program memory may occur if data memory and
program memory are stored physically in the same chip.
A problem with the Harvard architecture is that constant data (often lookup tables) must
be stored in the program memory because it is nonvolatile. This means that constants
cannot be read in the same way as volatile values from the data memory. Special “table
read” instructions must therefore be provided or part of the program memory is mapped
into data memory
The system is simpler and there is no difference between access to constant and
variable data.
Separate decoding logic is required, because separate buses and control signals are used
for accessing data memory and program memory
No additional logic is required because, Same bus and control signals are used for
accessing for both data memory and program memory.
Comparatively high cost Low cost

MEMORY MAPPED I/O & I/O MAPPED I/O :
I/O devices are mapped into the
system memory map. i.e Common
address space for memory and I/O
ports (The I/O ports are viewed as
memory locations and are addressed
likewise)
I/O devices are mapped into a
separate address space. i.e., there is
separate address space for memory
and I/O ports.

The control signals used for memory operation and I/O operation are
same.
M/IO = 1 for both Memory and I/O operations
Different control signals are used for memory and I/O
operations.
M/IO =1 for memory operation
M/IO =0 for I/O operation
All instruction which can access memory can be used to access I/O
ports.
Less no. of instructions are for I/O access. ( only IN and OUT
instructions)
The data can be moved from any register to I/O port and vice-versa.
The data transfer takes place between Accumulator and I/O port
only
The arithmetic, logic and bit manipulation instructions which are
available for data in memory can also be used for I/O operations.
Hence the processor can directly manipulate data from I/O port.
No instructions are available for direct manipulation of I/O data.
First the processor reads data from I/O port and then
manipulates.
Large number of I/O devices can be interfaced Less no. of I/O devices can be interfaced
Full address space can’t be used for addressing Memory, because some
locations are allotted for I/O ports.
Full address space can be used for addressing Memory, because
I/O locations are separated from memory.
The entire address bus must be fully decoded for every device, which
increases the cost
Less logic is needed to decode a discrete address and therefore
less cost

LITTLE-ENDIAN & BIG-ENDIAN PROCESSORS
Endianness specifies the order which the data is stored in the memory
by processor operations in a multi byte system.
2000H 2000H
2001H 2001H
2002H 2002H
2003H 2003H
Little-endian means lower order data byte is
stored in memory at the lowest address and
the higher order data byte at the highest
address.
Big-endian means the higher order data
byte is stored in memory at the lowest and
the lower order data byte at the highest
address.

INTRODUCTION TO MSP430 MICROCONTROLLERS:
• MAIN CHARACTERISTICS OF MSP430 MICROCONTROLLER
• Flash (or) ROM-based low-power MCUs
• CPU clock : 8/16 MHz
• Operating voltage : 1.8–3.6 V
• Power specification overview, as low as:
• 0.1 μA RAM retention
• 0.7 μA real-time clock mode operation
• 160 - 250 µA/MIPS at active operation
• Fast wake-up from standby mode in less than 1 µs.
• Device parameters
– Flash/ ROM options: 1 KB – 60 KB
– RAM options: 128 B– 8 KB
– GPIO options: 14 - 80 pins

INTRODUCTION TO MSP430 MICROCONTROLLERS:
• Other integrated peripherals:
• 10/12/16-bit Analogue-to-Digital Converter (ADC);
• 12-bit dual Digital-to-Analogue Converter (DAC);
• Comparator-gated Timers;
• Watch Dog Timer
• SPI, I2C, UART
• Operational Amplifiers (OP Amps)
• 16×16 multiplier
• Comparator_A
• Temp. sensor
• LCD driver
• Supply Voltage Supervisor (SVS)
• Brown out Reset
• 16 bit RISC CPU:
• Instructions processing on either bits, bytes or words;
• Compact core design reduces power consumption and cost;
• Compiler efficient;
• 27 core instructions;
• 7 addressing modes;
• Extensive vectored-interrupt capability.

BLOCK DIAGRAM OF MSP430 F2013/ F2003 MICROCONTROLLER

MSP430 part numbering:

VARIANTS OF MSP 430 FAMILY – 1XX, 2XX, 3XX, 4XX, 5XX:
VARIANT OF FAMILY POWER SPECIFICATIONS DEVICE PARAMETERS OTHER INTEGRATED PERIPHERALS
MSP430x1xx 0.1 μA RAM retention
0.7 μA real-time clock mode
200 μA / MIPS active
Features fast wake-up from standby mode in less than 6 µs.
Flash/ROM options: 1–60 KB
RAM options: 128 B– 2 KB
GPIO options: 14/22/48 pins
ADC options: Slope, 10 & 12-bit SAR
12-bit DAC, up to 2 16-bit timers, WDT, brown-out reset, SVS,
USART module (UART, SPI), DMA, 16×16 multiplier,
Comparator_A, Temp. sensor
MSP430F2xx 0.1 μA RAM retention
0.3 μA standby mode (VLO)
Feature ultra-fast wake-up from standby mode in less than 1 μs
Flash/ROM options: 1 KB–60 KB
RAM options: 128 B – 8 KB
GPIO options: 10/16/24/32/48 pins
ADC options: Slope, 10 & 12-bit SAR, 16 & 24-bit Sigma Delta
operational amplifiers, 12-bit DAC, up to 2 16-bit timers, watchdog
timer, brown-out reset, SVS, USI module (I²C, SPI), USCI module,
DMA, 16×16 multiplier, Comparator_A+, Temperature sensor
ROM options: 2–32 KB
RAM options: 512 B–1 KB
GPIO options: 14/40 pins
ADC options: Slope, 14-bit SAR
LCD controller, multiplier
Flash/ROM options: 4 KB– 60 KB
RAM options: 256 B – 8 KB
GPIO options: 14/32/48/56/68/72/80 pins
ADC options: Slope, 10 & 12-bit SAR, 16-bit Sigma Delta
12-bit DAC, Op Amps, RTC, up to two 16-bit timers, watchdog
timer, basic timer, brown-out reset, SVS, USART module (UART,
SPI), USCI module, LCD Controller, DMA, 16×16 & 32x32
multiplier, Comparator_A, Temp. sensor
Flash options: up to 512 KB
RAM options: up to 66 KB
ADC options: 10 & 12-bit SAR
GPIO options: 29/31/47/48/63/67/74/87 pins
High resolution PWM, 5 V I/O's, USB, backup battery switch, up to
4 16-bit timers, watchdog timer, Real-Time Clock, brown-out
reset, SVS, USCI module, DMA, 32x32 multiplier, Comp B,
temperature sensor
Flash options: up to 512 KB
RAM options: up to 66 KB
ADC options: 10 & 12-bit SAR
GPIO options: 74/90 pins
USB, LCD, DAC, Comparator_B, DMA, 32x32 multiplier, power
management module (BOR, SVS, SVM, LDO), watchdog timer, RTC,
Temp sensor

Memory map of MSP430

MSP430 –CPU architecture & registers
• The cpu features
– Calculated branching
– Table processing
– 27 RISC instructions
– 7 addressing modes
– All instructions use all the addressing modes
– Full register access
– Single cycle register operations (RISC)
– Direct memory-to-memory transfers
– Constant generator provides most used values

There are 16 registers
 Contents are 16-bits
 User has access to all
registers
 4 registers are special
purpose
Note bus structure
 MDB – Memory Data
Bus
 MAB – Memory Address
Bus
 Also have 2 internal
bussed to deliver 2
operand to ALU
Diagram is called the datapath
of the processor

• R4 thru R15
– Registers are indistinguishable
– Can be used as
• Data Registers
• Address Registers
• Index values
– Can be accessed with byte or word instructions
– There is Register-Byte operation and Byte-Register
operation – covered later

• R0: Program Counter (PC) :
• The 16-bit Program Counter (PC/R0) points to the
next instruction to be fetched from memory and
executed by the CPU.
• The Program counter is incremented by the number
of bytes used by the instruction (2, 4, or 6 bytes,
always even).

• R1: Stack Pointer (SP)
• The stack memory is a memory block where the
data is stored in LIFO manner.
• The Stack Pointer (SP/R1) holds the address of the
stack-top.
• In the MSP430, as in many other processors, the
stack is allocated at the top of the RAM and grows
down towards low addresses.

• Operation of the Stack :
The operation of the stack is illustrated in the
following figure. The specific addresses are for
MSO430F2013 with 128 Bytes of RAM are from
0x0200 to 0x027F. Hence, Before the execution, the
initially the value of SP = 0x0280

• R2: Status Register (SR)
• The Status Register (SR/R2) stores the status bits
and control bits.
• C : Carry Flag Z : Zero Flag
• N : Negative Flag V: Signed overflow flag

• Enable Interrupts :: Setting the general interrupt
enable (GIE) bit enables maskable interrupts.
• Clearing the bit disables all maskable interrupts.
• There are also nonmaskable interrupts, which
cannot be disabled with GIE.

• Control of Low-Power Modes :
• SCG1 (System clock generator 1) : When set, turns
off the SMCLK.
• SCG0 (System clock generator 0) : When set, turns
off the DCO dc generator, if DCO-CLK is not used for
MCLK or SMCLK.
• OSCOFF (Oscillator OFF ) : When set, turns off the
LF XT1 crystal oscillator,
• if LFXT1-CLK is not used for MCLK or SMCLK.
• CPUOFF : When set, turns off the CPU.

• R2/R3: Constant Generator Registers (CG1/CG2)
• Depending of the source-register addressing modes (As) value, six commonly used constants
can be generated without a code word or code memory access to retrieve them.
• The constants below are chosen based on the bit (As) of the instruction that selects the
addressing mode.
•
Register Addressing mode Constant
R2 10 +4
R2
11 +8
R3
00 0
R3
01 +1
R3
10 +2
R3
11 -1 (FFFF)

MSP430 –Addressing modes
• MSP430 addressing modes
– Addressing mode – the way in which the operand(s) of
an instruction are accessed, i.e., the effective addresses
are calculated.
– 7 modes supported
• Register Mode – (Rn) – operands are in registers
• Immediate Mode – #N – The operand is part of the
instruction
–Instructions have format OPCODE #OPERAND
• Absolute Mode – &ADDR – The address of the
operand is given by the word following the opcode
–Instructions have format OPCODE &ADDRESS

MSP430 –Addressing modes
• Remainder of addressing mode
– Indexed Mode – X(Rn) – (Rn+X) points to (is the address
of) the operand. The value X is the next word in the
instruction stream after the OPCODE.
– Symbolic Mode – ADDR – (PC+X) points to the operand.
X is the next word.
– Indirect Register Mode - @Rn – Rn is used as a pointer to
the operand.
– Indirect Autoincrement - @Rn+ - Rn is used as a pointer
to the operand. After access Rn is incremented by 1 for
.B instructions and by 2 for .W instructions

INSTRUCTION FORMATS OF MSP430 :
• Each instruction has 2- parts:
• The task to be performed – called as Operation code
(Opcode)
• The data to be operated on – called as Operand.
• Instruction format:
• There are three core-instruction formats:
»Dual-operand
»Single-operand
»Jump
OPCODE OPERAND

INSTRUCTION SET OF MSP430
• The instructions can be classified as follows:
1. Movement Instructions (Data Transfer)
2. Arithmetic and Logic Instructions
3. Shift and Rotate Instructions
4. Control Transfer instructions
(Branch/Subroutine/Interrupt)

Movement Instructions (Data Transfer)
Instruction Operation Example
1 mov.w src, dst
Copies data from source to destination
dst  src
mov.w R5, R6
R6  R5
2 push.w src
Push data onto stack
( first the SP is decremented by 2 and the source content is stored at stacktop)
@ --SP = src
push.w R5
SP  SP-2
@ SP  R5
3 pop.w dst
Pop data from stack
( first the content of stacktop is moved to destination and SP is incremented by
2)
dst = @SP + +
push.w R6
R6  @ SP
SP  SP+2

Arithmetic and Logic Instructions
1 add.w src, dst
Add the content of source to destination
dst  dst + src
add.w R5, R6
2 addc.w src, dst
Add with carry
dst  dst + (src + C)
addc.w R5, R6
3 adc.w dst
Add carry bit to the destination
dst  dst + C
adc.w R6
4 sub.w src, dst
Subtract the content of source from destination
dst  dst - src
sub.w R5, R6
5 subc.w src, dst
Subtract with borrow
dst  dst –( src + C)
subc.w R5, R6
6 sbc.w dst
Subtract borrow bit from the destination
dst  dst – C
sbc.w R6
7 cmp.w src,dst
Compares source and destination.
Performs ( dst – src), but Only flags are changed
If dst > src : C=0, Z=0
If dst < src : C=1, Z=0
If dst = src : C=0, Z=1
cmp.w R5,R6
Binary Arithmetic Instructions with Two operands

Arithmetic Instructions with One operand
1 clr.w dst
Clear destination
dst  0
clr.w R6
R6  0
2 dec.w dst
The content of destination is decremented by 1
dst  dst – 1
dec.w R6
R6  R6 - 1
3 decd.w dst
Double decrement
The content of destination is decremented by 2
dst  dst – 2
decd.w R6
R6  R6 – 2
4 inc.w dst
The content of destination is inccremented by 1
dst  dst + 1
inc.w R6
R6  R6 + 1
5 incd.w dst
Double increment
The content of destination is inccremented by 2
dst  dst + 2
incd.w R6
R6  R6 + 2
6 tst.w dst
Test ( compare with zero)
Performs ( dst – 0), but Only flags are changed
If dst > 0 : C=0, Z=0
If dst < 0 : C=1, Z=0
If dst = 0 : C=0, Z=1
tsd.w R6

Decimal Arithmetic & logical Instructions
1 dadd.w src, dst
Perfroms the decimal addtion of destination and source with carry
dst  dst + src + C
dadd.w R5, R6
R6  R6 + R5+C
2 dadc.w dst
Performs the decimal addition of destination and carry.
dst  dst + C
dadc.w R6
R6  R6 + C
These instructions are used to perform BCD addition
Logic Instructions with ONE operand
1 inv.w dst
Invert destination
Performs bit-wise NOT operation (1’s complement)
dst  ~dst
inv.w R6

Logic Instructions with Two operands
1 and.w src, dst
Performs bit-wise logic AND operation
dst  dst AND src
and.w R5, R6
2 xor.w src, dst
Performs bit-wise logic Ex-OR operation
dst  dst XOR src
xor.w R5, R6
3 bit.w src, dst
Performs bit-wise Test operation
It performs Logic AND operation, But Only flags are affected
bit.w R5, R6
4 bis.w src, dst
Set bits in destination
The source operand and the destination operand are logically ORed. The result is placed
into the destination. The source operand is not affected.
dst  dst OR src
bis.w R5, R6
5 bic.w src, dst
Clear bits in destination
The inverted source operand and the destination operand are logically ANDed. The result
is placed into the destination. The source operand is not affected
dst  dst AND ~src
bic.w R5, R6

Byte manipulation
1 swpb dst
Swap upper and lower bytes
The high and the low byte of the operand are exchanged
dst.15:8 ↔ dst.7:0
swpb R6
2 sxt dst
Extend sign of lower byte
The sign of the low byte of the operand is extended into the high byte
dst. 15:8  dst.7
If dst.7 = 0: high byte = 00 H afterwards
If dst.7 = 1: high byte = FF H afterwards
sxt R6

Operations on Bits in Status Register
Instruction Operation Flag affected
1 clrc Clear Carry bit C = 0
2 clrn Clear Negative bit N = 0
3 clrz Clear Zero bit Z = 0
4 setc Set Carry bit C = 1
5 setn Set Negative bit N = 1
6 setz Set Zero bit Z = 1
7 dint Disable General Interrupts GIE = 0
8 eint Enable General Interrupts GIE = 1
These instructions are used to set or clear the flags in Status Register. All these
instructions are emulated instructions.

Shift and Rotate Instructions
Instruction Description Operation
rla dst Arithmetic shift Left
rra dst Arithmetic shift Right
rlc dst Rotate Left through Carry
rrc dst Rotate Right through Carry

Control Transfer Instructions
Instruction Description Operation
1 br src Branch ( go to) PC  src
2 call src Call Subroutine
SP  SP-2
@ SP  PC
PC  src
3 ret Return from Subroutine
PC  @ SP
SP  SP+2
4 reti
Return from Interrupt
SR  @ SP
SP  SP+2
PC  @ SP
SP  SP+2
5 nop
No operation
( consumes single cycle )

JUMP Instructions
1 jmp label Unconditional Jump
2 jc / jlo label Jump if carry / Jump if lower Jump if C =1
3 jnc / jhs label Jump if not carry / Jump higher or same Jump if C =0
4 Jz / jeq label Jump if zero / Jump if equal Jump if Z =1
5 Jnz / jne label Jump if not zero / Jump if not equal Jump if Z =0
6 jn label Jumpif negative Jump if N =1
7 jge label Jump if greater or equal (signed values) Jump if (N xor V) =0
8 jl label Jump if less than (signed values) Jump if (N xor V) =1

Sample Embedded system on MSP430

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