MICROCONTROLLER 8051

1. Pune Vidyarthi Griha’s
COLLEGE OF ENGINEERING, NASHIK – 3.
“8051 MICROCONTROLLER”
By
Prof. Anand N. Gharu
(Assistant Professor)
PVGCOE Computer Dept.
27th August 2017
.

2. Contents
• Introduction
• Comparision
• Features
• Architecture
• Pin description
• Programming Model - SFR
• Addressing modes
• Intruction set
• Timer and control
• Serial communication
• interrupts

3. Introduction
• The microprocessor also known as the central
processing unit, is the brain of all computers and
many household and electronic devices.
Multiple microprocessors, working together, are
the "hearts" of datacenters, super-computers,
communications products, and other digital
devices.

4. History
• Fairchild Semiconductors (founded in 1957) invented
the first IC in 1959.
• In 1968, Robert Noyce, Gordan Moore, Andrew
Grove resigned from Fairchild Semiconductors.
• They founded their own company Intel (Integrated
Electronics).
• The first microprocessor invented was of 4-bit, after
that 8-bit,16-bit,.32-bit & 64-bit are founded

5. History
 4-bit microprocessor
• Intel 4004
• Intel 4040
8-bit microprocessor
• Intel 8008
• Intel 8080
• Intel 8085
16-bit microprocessor
• Intel 8086
• Intel 8088
• Intel 80186 & 80188

6. History
• Intel 80286
32-bit microprocessor
• Intel 80386
• Intel 80486
• Intel pentium
• Intel pentium pro
• Intel pentium II
• Intel pentium II xeon
• Intel pentium III
• Intel pentium IV
• Intel dual core

7. History
 64-bit microprocessors
• Intel core 2
• Intel core i7
• Intel core i5
• Intel core i3

8. Microprocessor (MPU)
• MPU (CPU)
o Read instructions
o Process binary data
330_018

9. Microcontroller

10. Micro controller
• A self-contained system in which a processor,
support, memory, and input/output (I/O) are all
contained in a single package.
• A small computer system on a single IC
10

11. History of Microcontroller
• First used in 1975(Intel 8048)
• The introduction of EEPROM in 1993, allowed
microcontrollers to be electrically erased
• The same year, Atmel introduced the first
microcontroller using Flash memory.

12. Microcontroller

13. Types of microcontroller

14. Basic microcontroller architecture

15. Difference between microprocessor
& microcontroller
Microprocessor Microcontroller
Contains ALU, general purpose register, stack
pointer, programme counter, clock timing &
interrupt circuit
Contains the circuitary of microprocessor & in
addition it has built in ROM, I/O devices, timer
& counter
It has too many instructions to move the data
between CPU & memory
It has one or two instruction to move the data
between CPU & memory
It has one or two bit handling instruction It has many bit handling instruction
Access time for memory & I/O devices is more Less access time for built in memory & I/O
devices
Microprocessor based system requires more
hardware
Microcontroller based system requires less
hardware, reducing PCB size & increasing the
reliability
More flexible in design point of view Less flexible in design point of view
It has single memory map for data & code It has separate memory map for data & code
Less number of pins are malfunctioned More number of pins are malfunctioned

17. Disadvantages of microprocessor
• The overall system cost is high
• A large sized PCB is required for assembling
all the components
• Overall product design requires more time
• Physical size of the product is big
• A discrete components are used, the system is
not reliable
SJCET

18. Advantages of Microcontroller
based System
• As the peripherals are integrated into a single chip,
the overall system cost is very less
• The product is of small size compared to micro
processor based system
• The system design now requires very little efforts
• As the peripherals are integrated with a
microprocessor the system is more reliable
• Though microcontroller may have on chip
ROM,RAM and I/O ports, addition ROM, RAM I/O
ports may be interfaced externally if required
• On chip ROM provide a software security

19. Salient Features
(1). 8 bit microcontroller originally developed by Intel in 1980.
(2). High-performance CMOS Technology.
(3). Contains Total 40 pins.
(4). Address bus is of 16 bit & data bus is of 8 bit.
(5). 4K bytes internal ROM (program).
(6). 128 bytes internal RAM (data).
(7). Four 8-bit I/O ports.
(8). Two 16-bit timers.
(9). Serial interface Communication.
(10). 64K external code & data memory space.
(11). 210 bit-addressable locations.
(12). Internal memory consists of on-chip ROM and on-chip data RAM.
(13). 8051 implements a separate memory space for programs (code) and data.
(14). Operating frequency is 24MHz-33MHz.
(15). +5V Regulated DC power supply is required to operate .
(16). It has four 8 bit ports, total 32 I/O lines.
(17). RAM, ROM, I/O ports, one serial port and timers are all on-chip.
(18). 6-interrupts (2 are external with 2 priority levels).
(19). Low-power Idle and Power-down Modes.
(20). Full duplex UART.
(21). 8051 has 21 special function registers (SFRs).
19

20. 8051 Block Diagram
20

21. 21

22. PROGRAM STATUS WORD
(PSW)
22
CY AC F0 RS1 RS0 OV P
RS
0
R
S1
BANK SELECTION
0 0 00H – 07H BANK0
0 1 08H – 0FH BANK 1
1 0 10H – 17H BANK2
1 1 18H – 1FH BANK 3

23. Memory Organization
• The 8051 memory organization is rather complex.
• The 8051 has separate address spaces for Program
Memory, Data Memory, and external RAM.
• This is refereed to as a Harvard architecture.
• Both program memory and external data memory are
8 bits wide and use 16 bits of address. The internal
data memory is accessed using an 8-bit address.
23

24. Memory Structure of 8051
24

25. Data memory map 8051
25

26. Internal Memory Organization
26
4 register
bank of each
8 bytes
General
purpose
RAM area
Bit
addressable
RAM area

27. Internal Memory
(1). 8051 implements a separate memory space for programs (code) and data.
(2). Both code and data may be internal, however, both expand using external
components to a maximum of 64K code memory and 64K data memory.
(3). Internal memory consists of on-chip ROM and on-chip data RAM.
(4). On-chip RAM contains a rich arrangement of general purpose storage, bit
addressable storage, register banks, and special function registers.
(5). In the 8051, the registers and input/output ports are memory mapped and
accessible like any other memory location.
(6). In the 8051, the stack resides within the internal RAM, rather than in external
RAM.
27

28. 28
Register RAM memory Allocation in
8051

29. 29
4-Register banks in the 8051
Microcontroller

30. Special Function Registers
(1). ACC
(2). B
(3). PSW
(4). SP
(5). DPTR
(5). IP
(6). PMODE
(7). PCON
(8). TMODE
(9). TCON etc. 30

31. (1). 8051 has 21 special function registers (SFRs) at the top of internal
RAM from address 80H to FFH.
(2). Most of the addresses from 80H to FFH are not defined, except for 21
of them.
(3). Some SFR’s are both bit-addressable and byte addressable, depending
on the instruction accessing the register.
(4). This area consists of a series of memory-mapped ports and registers.
(5). All 8051 CPU registers, I/O ports, timers and other architecture
components are accessible in 8051 C through SFRs
31
Special Function Registers

32. B Register
(1). B register or accumulator B is used along with the
accumulator for multiply and divide operations.
(2). MUL AB: multiplies 8 bit unsigned values in A and B.
and leaves the 16 bit result in A (low byte) and B (high
byte).
(3). DIV AB: divided A by B, leaving the integer result in A
and remainder in B.
(4). B register is bit-addressable.
32

33. 33
PSW (Program Status word) / Flag Register

34. (1). Stack pointer (SP) is an 8-bit register at address 81H.
(2). It contains the address of the data item currently on top of the
stack.
(3). Stack operations include pushing data on the stack
andpopping data off the stack.
(4). Pushing increments SP before writing the data
(5). Popping from the stack reads the data and decrements the SP
(6). 8051 stack is kept in the internal RAM
(7). Depending on the initial value of the SP, stack can have
different sizes
(8). Example: MOV SP,#5FH
(9). On 8051 this would limit the stack to 32 bytes since the
uppermost address of on chip RAM is 7FH.
Stack Pointer
34

35. Data pointer (DPTR)
(1). Data pointer (DPTR): is used to access external data or code.
(2). DPTR is a 16 bit register at addresses 82H (low byte) and 83H (high
byte).
(3). The data pointer is used in operations regarding external RAM and
some instructions involving code memory.
(4). Example: the following instructions write 55H into external RAM
location 1000H:
• MOV A,#55H
• MOV DPTR,#1000H
• MOVX @DPTR,A 35

36. I/O Ports
(1). One of the major features of a microcontroller is the versatility built
into the I/O circuits that connect the microcontroller to the outside
world .
(2). To be commercially viable, the 8051 had to incorporate as many I/O
functions as were technically and economically possible.
(3). One of the most useful features of the 8051 is four bidirectional I/O
ports.
(4). Each port has an 8-bit latch in the SFR space as mentioned earlier.
(5). To reduce the overall package pin count, the 8051 employs multiple
functions for each port.
(6). Each port also has an output drive and an input buffer.
(7). These ports can be used to general purpose I/O, as an address and
data lines.
(8). The four 8-bit I/O ports P0, P1, P2 and P3 each uses 8 pins 36

37. I/O Ports
37

38. PORT 0
(1). Port 0 is 8-bitbidirectional I/O port.
(2). Port 0 pins can be used as high-impedance inputs.
(3). Port 0 is also the multiplexed low-order address and data bus
during accesses to external program and data memory.
(4). We r using pins no. from 32 to 39.
(5). When used as an output the pin latches are programmed to
0.
(5). When used as an input the pin latches are programmed to 1.
38

39. (1). Port 1 is an 8-bit bidirectional I/0 port.
(2). We r using pins no. from 1 to 9.
(3). Port 1 have no dual functions.
(4). When used as an output the pin latches are programmed to 0.
(5). When used as an input the pin latches are programmed to 1.
PORT 1
39

40. (1). Port 2 is an 8-bit bidirectional I/O port.
(2). Port 2 emits the high-order address byte during fetches from
external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR).
(3). When used as an output the pin latches are programmed to 0.
(4). When used as an input the pin latches are programmed to 1.
(5). We r using pins no. from 21 to 28.
PORT 2
40

41. (1). Port 3 is an 8-bit bi-directional I/0 port.
(2). We r using pins no. from 10 to 17.
• RXD (P3.0): Serial input port,
• TXD (P3.1): Serial output port,
• INT0 (P3.2): External interrupt,
• INT1 (P3.3): External interrupt,
• T0 T0 (P3.4): Timer 0 external input,
• T1 (P3.5): Timer 1 external input,
• WR (P3.6): External data memory write strobe,
• RD (P3.7): External data memory read strobe,
PORT 3
41

42. Pin Diagram of 8051
42

43. IMPORTANT PINS (IO Ports)
• Port 0
pins 32-39 （P0.0～P0.7）
o 8-bit R/W - General Purpose I/O
o Or acts as a multiplexed low byte
address and data bus for external
memory design
One of the most useful features of the 8051 is that it contains
four I/O ports (P0 - P3)
Each port can be used as input or output (bi-direction)

44. IMPORTANT PINS (IO Ports)
• Port 1
（pins 1-8） （P1.0～P1.7）
o Only 8-bit R/W - General Purpose
I/O

45. IMPORTANT PINS (IO Ports)
• Port 2
• （pins 21-28（P2.0～P2.7）
o 8-bit R/W - General Purpose
I/O
o Or high byte of the address
bus for external memory
design

46. IMPORTANT PINS (IO Ports)
• Port 3
• （pins 10-17 （P3.0～P3.7）
o General Purpose I/O
o if not using any of the internal
peripherals (timers) or external
interrupts.

47. Port 3 Alternate Functions

48. • ALE - Address latch enable
to select valid address4
• EA/Vpp - External access enable
EA-0 execute program in external memory
EA-1 execute program in internal memory
• Vpp - it receives 21 V for on chip EPROM
* PSEN - Program store enable
store to read the external program memory

49. 8051 Addressing modes
• Addressing Modes
o Register addressing
o Direct addressing
o Indirect addressing
o Immediate constant addressing
o Relative addressing
o Absolute addressing
o Long addressing
o Indexed addressing

50. Introduction
• A computer instruction is made up of an operation code (op-code)
followed by either zero, one or two bytes of operands
• The op-code identifies the type of operation to be performed while
the operands identify the source and destination of the data
• The operand can be:
o The data value itself
o A CPU register
o A memory location
o An I/O port
• If the instruction is associated with more than one operand, the
format is always:
Instruction Destination, Source

51. Addressing Modes
• Eight modes of addressing are available with the C8051F020
• The different addressing modes determine how the operand
byte is selected
Addressing Modes Instruction
Register MOV A, B
Direct MOV 30H,A
Indirect ADD A,@R0
Immediate Constant ADD A,#80H
Relative* SJMP AHEAD
Absolute* AJMP BACK
Long* LJMP FAR_AHEAD
Indexed MOVC A,@A+PC
* Related to program branching instructions

52. Register Addressing
• The register addressing instruction involves information
transfer between registers
• Example:
MOV R0, A
• The instruction transfers the accumulator content into the
R0 register. The register bank (Bank 0, 1, 2 or 3) must be
specified prior to this instruction.

53. Direct Addressing
• This mode allows you to specify the operand by giving its actual
memory address (typically specified in hexadecimal format) or by
giving its abbreviated name (e.g. P3)
Note: Abbreviated SFR names are defined in the “C8051F020.inc”
header file
• Example:
MOV A, P3 ;Transfer the contents of
;Port 3 to the accumulator
MOV A, 020H ;Transfer the contents of RAM
;location 20H to the accumulator

54. Indirect Addressing
• This mode uses a pointer to hold the effective address of the
operand
• Only registers R0, R1 and DPTR can be used as the pointer
registers
• The R0 and R1 registers can hold an 8-bit address, whereas DPTR
can hold a 16-bit address
• Examples:
MOV @R0,A ;Store the content of
;accumulator into the memory
;location pointed to by
;register R0. R0 could have an
;8-bit address, such as 60H.
MOVX A,@DPTR ;Transfer the contents from
;the memory location
;pointed to by DPTR into the
;accumulator. DPTR could have a
;16-bit address, such as 1234H.

55. Immediate Addressing
• This mode of addressing uses either an 8- or 16-bit constant value as
the source operand
• This constant is specified in the instruction, rather than in a register
or a memory location
• The destination register should hold the same data size which is
specified by the source operand
• Examples:
ADD A,#030H ;Add 8-bit value of 30H to
;the accumulator register
;(which is an 8-bit register).
MOV DPTR,#0FE00H ;Move 16-bit data constant
;FE00H into the 16-bit Data
;Pointer Register.

56. Relative Addressing
• This mode of addressing is used with some type of jump
instructions, like SJMP (short jump) and conditional jumps like
JNZ
• These instructions transfer control from one part of a program to
another
• The destination address must be within -128 and +127 bytes from
the current instruction address because an 8-bit offset is used (28 =
256)
• Example:
GoBack: DEC A ;Decrement A
JNZ GoBack ;If A is not zero, loop
back

57. Absolute Addressing
• Two instructions associated with this mode of addressing are ACALL
and AJMP instructions
• These are 2-byte instructions where the 11-bit absolute address is
specified as the operand
• The upper 5 bits of the 16-bit PC address are not modified. The lower
11 bits are loaded from this instruction. So, the branch address must be
within the current 2K byte page of program memory (211 = 2048)
• Example:
ACALL PORT_INIT ;PORT_INIT should be
;located within 2k bytes.
PORT_INIT: MOV P0, #0FH ;PORT_INIT subroutine

58. Long Addressing
• This mode of addressing is used with the LCALL and LJMP
instructions
• It is a 3-byte instruction and the last 2 bytes specify a 16-bit destination
location where the program branches
• It allows use of the full 64 K code space
• The program will always branch to the same location no matter where
the program was previously
• Example:
LCALL TIMER_INIT ;TIMER_INIT address (16-bits
;long) is specified as the
;operand; In C, this will be a
;function call: Timer_Init().
TIMER_INIT: ORL TMOD,#01H ;TIMER_INIT subroutine

59. Indexed Addressing
• The Indexed addressing is useful when there is a need to retrieve data from a
look-up table
• A 16-bit register (data pointer) holds the base address and the accumulator
holds an 8-bit displacement or index value
• The sum of these two registers forms the effective address for a JMP or
MOVC instruction
• Example:
MOV A,#08H ;Offset from table start
MOV DPTR,#01F00H ;Table start address
MOVC A,@A+DPTR ;Gets target value from the table
;start address + offset and puts it
;in A.
• After the execution of the above instructions, the program will branch to
address 1F08H (1F00H+08H) and transfer into the accumulator the data
byte retrieved from that location (from the look-up table)

60. 8051 Instruction

61. Instruction Types
• The C8051F020 instructions are divided into five
functional groups:
o Arithmetic operations
o Logical operations
o Data transfer operations
o Boolean variable operations
o Program branching operations

62. Arithmetic Operations
• With arithmetic instructions, the C8051F020 CPU has no special knowledge of
the data format (e.g. signed binary, unsigned binary, binary coded decimal,
ASCII, etc.)
• The appropriate status bits in the PSW are set when specific conditions are met,
which allows the user software to manage the different data formats
 [@Ri] implies contents of
memory location pointed to by
R0 or R1
 Rn refers to registers R0-R7 of
the currently selected register
bank

63. Logical Operations
• Logical instructions perform
Boolean operations (AND, OR,
XOR, and NOT) on data bytes
on a bit-by-bit basis
• Examples:
ANL A, #02H ;Mask bit 1
ORL TCON, A
;TCON=TCON-OR-A

64. Data Transfer Instructions
• Data transfer instructions can be
used to transfer data between an
internal RAM location and an
SFR location without going
through the accumulator
• It is also possible to transfer
data between the internal and
external RAM by using indirect
addressing
• The upper 128 bytes of data
RAM are accessed only by
indirect addressing and the
SFRs are accessed only by
direct addressing
Mnemonic Description
MOV @Ri, direct [@Ri] = [direct]
MOV @Ri, #data [@Ri] = immediate data
MOV DPTR, #data 16 [DPTR] = immediate data
MOVC A,@A+DPTR A = Code byte from [@A+DPTR]
MOVC A,@A+PC A = Code byte from [@A+PC]
MOVX A,@Ri A = Data byte from external ram [@Ri]
MOVX A,@DPTR A = Data byte from external ram [@DPTR]
MOVX @Ri, A External[@Ri] = A
MOVX @DPTR,A External[@DPTR] = A
PUSH direct Push into stack
POP direct Pop from stack
XCH A,Rn A = [Rn], [Rn] = A
XCH A, direct A = [direct], [direct] = A
XCH A, @Ri A = [@Rn], [@Rn] = A
XCHD A,@Ri Exchange low order digits

65. Boolean Variable Instructions
• The C8051F020 processor can
perform single bit operations
• The operations include set, clear,
and, or and complement instructions
• Also included are bit–level moves or
conditional jump instructions
• All bit accesses use direct addressing
• Examples:
SETB TR0 ;Start Timer0.
POLL:JNB TR0, POLL ;Wait
till timer overflows.
Mnemonic Description
CLR C Clear C
CLR bit Clear direct bit
SETB C Set C
SETB bit Set direct bit
CPL C Complement c
CPL bit Complement direct bit
ANL C,bit AND bit with C
ANL C,/bit AND NOT bit with C
ORL C,bit OR bit with C
ORL C,/bit OR NOT bit with C
MOV C,bit MOV bit to C
MOV bit,C MOV C to bit
JC rel Jump if C set
JNC rel Jump if C not set
JB bit,rel Jump if specified bit set
JNB bit,rel Jump if specified bit not set
JBC bit,rel
if specified bit set then clear it and
jump

66. Program Branching Instructions
• Program branching
instructions are used to
control the flow of
program execution
• Some instructions provide
decision making
capabilities before
transferring control to
other parts of the program
(conditional branches).
Mnemonic Description
ACALL addr11 Absolute subroutine call
LCALL addr16 Long subroutine call
RET Return from subroutine
RETI Return from interrupt
AJMP addr11 Absolute jump
LJMP addr16 Long jump
SJMP rel Short jump
JMP @A+DPTR Jump indirect
JZ rel Jump if A=0
JNZ rel Jump if A NOT=0
CJNE A,direct,rel
Compare and Jump if Not Equal
CJNE A,#data,rel
CJNE Rn,#data,rel
CJNE @Ri,#data,rel
DJNZ Rn,rel
Decrement and Jump if Not Zero
DJNZ direct,rel
NOP No Operation

67. Timers and Counters
(1). Many microcontroller applications require the counting of external events, such as
frequency of a pulse train, or the generation of precise internal time delays
between actions.
(2). Both of these tasks can be accomplished using software techniques.
(3). The 8051 has two 16-bit registers that can be used as either timers or counters.
(4). These two up counters are name T0 and T1 and are provided for general use of
the programmer.
(5). Each counter may be programmed to count internal clock pulses, act as a timer, or
programmed to count external events as a counter.
(6). The counters are divided into two 8-bit registers called the timer low (TL0, TL1)
and timer high (TH0, TH1) bytes. 67

68. TCON (Timer/Counter Control
Register)
68

69. TMOD (Timer/Counter Control Register)
69

70. SCON (Serial Port Control Register)
70

71. PCON (Power Mode Control Register)
71

72. Interrupts
• An interrupt is a special feature which Allows the 8051 to provide the illusion of
"multitasking,“ although in reality the 8051 is only doing one thing at a time. The
word "interrupt" can often be substituted with the word "event.“
• An interrupt is triggered whenever corresponding event occurs. When the event
occurs, the 8051 temporarily puts "on hold" the normal execution of the program
and executes a special section of code referred to as an interrupt handler.
• Whenever any device needs its service, the device notifies the microcontroller by
sending it an interrupt signal.
• There are total 5 interrupt sources in 8051 Microprocessor as follows.
(1). Timer Flag 0, (2). Timer Flag 1, (TF1 & TF2 are Timer Flag Interrupts).
(3). INT 0, (4). INT 1, (INT 0 & INT 1 are external interrupts).
(5). Serial Port Interrupt (RI or TI).
72

73. Interrupts Priorities
Interrupt
Destinations
Interrupt Address
(Hex)
1 IE0 0003H
2 TF0 000BH
3 IE1 0013H
4 TF1 001BH
5 SERIAL 0023H 73

74. Interrupt Priority (IP) SFR
74

75. Interrupt Enable (IE) SFR
75

76. Thank You
8/27/2017 76