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ONFI 3.0 NAND Flash Controller

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Arasan Chip Systems

The document introduces the ONFI 3.0 NAND flash controller standard. It features faster data transfer speeds up to 200MT/s using differential signaling and DDR-2. It allows for dynamically scalable error correction and supports new commands. Arasan provides a fully compliant ONFI 3.0 controller core along with documentation, models, and verification IP to help customers integrate it into their designs.

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Introducing the ONFI 3.0 NAND Flash Controller By Dennis McCarty
Arasan Chip Systems Total IP Solutions ONFI 3.0 Features Core Architecture Deliverables Arasan Advantages ©Arasan Chip Systems Inc. 2011
Arasan Total IP Solutions ©Arasan Chip Systems Inc. 2011
ONFI Background ONFI Open NAND Flash Interface • NAND Flash Industry Consortium Version 3.0 • Latest specification for NAND Flash control • Faster data transfers and new features • Backwards compatible with previous versions ©Arasan Chip Systems Inc. 2011
ONFI 3.0 Features Operates memory devices at any frequency up to 200 MHz • 200 MT/S Differential signaling on clock and data lines DDR-2 Transfers • True and Complement Data Strobes • SDR, NV-DDR and NV-DDR2 ©Arasan Chip Systems Inc. 2011
ONFI 3.0 Features Single and Dual data bus discovery Eight chip enables Page sizes up to 8K ECC up to 64 bits • Dynamically configurable ECC width Warm-up cycles for high-speed operation Supports all new commands ©Arasan Chip Systems Inc. 2011
Patented BCH Coding BCH Coded ECC supports dynamically scalable correction bits Parallel bit processing on the BCH encoder Parallel syndrome generation Inversion-less Berlekamp-Massey algorithm for key equation solver Parallel computation for the key equation solver Parallel Chien search algorithm ©Arasan Chip Systems Inc. 2011
NAND Flash Architecture ©Arasan Chip Systems Inc. 2011
ONFI Compliance Compliant to the 3.0 ONFI (rev. 2011) Only announced product in the market ©Arasan Chip Systems Inc. 2011
Deliverables RMM (Reuse Methodology Manual) compliant Verilog Configurable Behavioral models Verification Suite & Test Cases Documentation and Design Support ©Arasan Chip Systems Inc. 2011
Total IP Solutions Features • Analog and Digital cores, with no gaskets or wrappers for efficient, low-gate design • Software, Synthesis scripts and Test Environments • Verification IP, ESL models • HW Development Kits & Verification Platforms • Design Services ©Arasan Chip Systems Inc. 2011
Total IP Solutions Benefits • Compliance across the standard • Single supplier – Single support • Guaranteed compatibility • Lowest overall cost and risk • Seamless integration from PHY to SW layers • Fastest cycle: MRD to SoC ©Arasan Chip Systems Inc. 2011

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ONFI 3.0 NAND Flash Controller

  • 1. Introducing the ONFI 3.0 NAND Flash Controller By Dennis McCarty
  • 2. Arasan Chip Systems Total IP Solutions ONFI 3.0 Features Core Architecture Deliverables Arasan Advantages ©Arasan Chip Systems Inc. 2011
  • 3. Arasan Total IP Solutions ©Arasan Chip Systems Inc. 2011
  • 4. ONFI Background ONFI Open NAND Flash Interface • NAND Flash Industry Consortium Version 3.0 • Latest specification for NAND Flash control • Faster data transfers and new features • Backwards compatible with previous versions ©Arasan Chip Systems Inc. 2011
  • 5. ONFI 3.0 Features Operates memory devices at any frequency up to 200 MHz • 200 MT/S Differential signaling on clock and data lines DDR-2 Transfers • True and Complement Data Strobes • SDR, NV-DDR and NV-DDR2 ©Arasan Chip Systems Inc. 2011
  • 6. ONFI 3.0 Features Single and Dual data bus discovery Eight chip enables Page sizes up to 8K ECC up to 64 bits • Dynamically configurable ECC width Warm-up cycles for high-speed operation Supports all new commands ©Arasan Chip Systems Inc. 2011
  • 7. Patented BCH Coding BCH Coded ECC supports dynamically scalable correction bits Parallel bit processing on the BCH encoder Parallel syndrome generation Inversion-less Berlekamp-Massey algorithm for key equation solver Parallel computation for the key equation solver Parallel Chien search algorithm ©Arasan Chip Systems Inc. 2011
  • 8. NAND Flash Architecture ©Arasan Chip Systems Inc. 2011
  • 9. ONFI Compliance Compliant to the 3.0 ONFI (rev. 2011) Only announced product in the market ©Arasan Chip Systems Inc. 2011
  • 10. Deliverables RMM (Reuse Methodology Manual) compliant Verilog Configurable Behavioral models Verification Suite & Test Cases Documentation and Design Support ©Arasan Chip Systems Inc. 2011
  • 11. Total IP Solutions Features • Analog and Digital cores, with no gaskets or wrappers for efficient, low-gate design • Software, Synthesis scripts and Test Environments • Verification IP, ESL models • HW Development Kits & Verification Platforms • Design Services ©Arasan Chip Systems Inc. 2011
  • 12. Total IP Solutions Benefits • Compliance across the standard • Single supplier – Single support • Guaranteed compatibility • Lowest overall cost and risk • Seamless integration from PHY to SW layers • Fastest cycle: MRD to SoC ©Arasan Chip Systems Inc. 2011