opamp limitations

1. Signals and
Electronic
System Design
Limitations of
Operational Amplifiers
© Linear
Mario Mata
mario.mata@gcu.ac.uk
M204

2. 2 Signals and electronic systems design
M Mata
Contents
• Input currents
• Closed-loop input and output impedances
• Slew rate
• OpAmps open-loop and closed-loop bandwidths
– GBW product
• Dynamic performance of amplifiers
– Effects of capacitive coupling
– Effects of parasitic series L and shunt C
– Effect on pulse response
• Linear and nonlinear distortion
– Total Harmonic Distortion (THD)
• Stability: Phase margin. Compensation
• Driving capacitive loads

3. 3 Signals and electronic systems design
M Mata
Input currents
• The input terminals of OpAmps are connected to the base (or gate) of
the input stage transistors (thus the large input impedance Rin)
• But this also means that some input current must be present to set up
the bias point of the internal transistors
i+
i- i-
i+
• Assuming i+,i- ~ 0 in calculations implies that the feedback current iF
needs to be iF >> i+,i- : iF ~mA for BJT-based OpAmps, or nA for FET-
based ones. This limits practical values for R1, RF
• The OpAmp datasheet gives values for the average of both input
currents (input bias current) and also for the unbalance (difference)
between them (input offset current):
BJT-based OpAmps: iB~80nA, ioffs~20nA
FET-based OpAmps: iB~50pA, ioffs~20pA

4. 4 Signals and electronic systems design
M Mata
Input currents compensation
• The effect of these currents is relevant when working near Vin=0V.
Then ideally VO=0V, and feedback current iF~0A as well.
As VO~0, input current i- is flowing
by the shunt of R1 and RF
Vo~0V
R1
Vin=0V
RF
Rin
+
-
i+
i-
R1 RF
Vo~0V
i-
V-
This unbalances the input:
Which in turn makes VO≠0V:
• This is easily compensated by causing a similar unbalance in V+ by
inserting a compensation resistor RCOMP=R1||RF at this input:
R1
Vin
RF
Rin
+
-
i+
i-
RCOMP
This which works as long as i+ ≈ i-
In practice it compensates for the input bias current iB,
but is still affected by the (smaller) unbalance ioffs = |i+- i-|

5. 5 Signals and electronic systems design
M Mata
Design Example
Add the corresponding input current compensation resistors to the
following amplifier stages:
10kW
10kW
VO
VIN
VIN
VO
10kW
100kW

6. 6 Signals and electronic systems design
M Mata
Input and output impedances
• By design, OpAmps show:
• A very large input impedance Rin
• Rin~107 for BJT-based OpAmps
• Rin~109 for FET-based OpAmps
• A low output impedance RO
• Typically RO~50W
• When used for linear applications (in closed-loop circuits)
the feedback loop can also improve the overall input and
output impedances

7. 7 Signals and electronic systems design
M Mata
Closed-Loop Input Impedance
Closed-loop input impedance for the non-inverting amplifier:
Vo
R1
Vin
Rf
Rin
Zin
+
-
Ro
iin
Vin
RF
+
-
R1
Vo

AOL
Feedback ratio
As AOL>>1:
ACL=1/ Closed-loop impedance is larger than Rin!
As AOL = AOL/ACL >> 1:

8. 8 Signals and electronic systems design
M Mata
Closed-Loop Input Impedance
Closed-loop input impedance for the inverting amplifier
Vin
+
-
R1
Vo
RF
AOL
iin
iF
Rin
i-
as long as we keep iF>>i-
(R1,RF<<Rin)
As AOLR1>>R1+RF:
ACL = 1 - 1/
As AOLR1>>R1+RF:
Closed-loop impedance is just R1

9. 9 Signals and electronic systems design
M Mata
Closed-Loop Output Impedance
Closed-loop output impedance for non-inverting amp
Typ AOL~106, R0 ~50 to 100 W
Notice that output impedance is the same for the inverting amplifier
Closed-loop output impedance is reduced below R0
R1
RF
Rin
Ro
+
-
io
VO
𝑉 = 𝐴 𝑉 − 𝑉 O
O
CL
O
i
V
Z 
)
(
Feedback ratio
As RO<<(1+ AOL)(R1+RF):

10. 10 Signals and electronic systems design
M Mata
Design example
Design an inverting amplifier with a
closed-loop gain of -10, having an
input impedance of at least 10kW
Vs
Vo
Rf
R1
RC
+
-
The closed-loop voltage gain is given by:
As the input impedance is Zin(CL)~R1:
We may then take for instance and then solve for RF:

11. 11 Signals and electronic systems design
M Mata
Design Example
An op-amp non-inverting amplifier is used as a pre-amp having a closed-
loop gain ACL = 10.
To match impedances to those required by the previous and posterior
circuits, the amplifier must present input and output impedances of 50W.
Suggest what additional components will be required to achieve this. Draw
the resulting circuit.

12. 12 Signals and electronic systems design
M Mata
Slew rate
The output of an operational amplifier cannot change instantly. This is
especially relevant for step-like and square signals
If the input changes suddenly, the output will change “as fast as possible”.
The parameter measuring the maximum rate of change of the output is
the Slew Rate (SR), usually measured in V/ms. Example:
Typical SR values are around 0.5V/ms
t
Vin
VO=5Vin
1ms
SR V
Ideal output
For instance, if Vin goes from 0V to 1V and the gain ACL is 5:
• The output final value will be VO = 5Vin = 5V
• But it will take some time for the output to reach this final value:
𝑡 → =
Δ𝑉
𝑆𝑅
=
5 − 0 𝑉
0.5 𝑉/𝜇𝑠
= 10𝜇𝑠
If the period of the signal is small, this effect is a limiting factor. I.e. f=50kHz 
T=20ms  the rise time is already half the period!
Real output

13. 13 Signals and electronic systems design
M Mata
OpAmp bandwidth – internal compensation
• OpAmps are designed to present a huge open-loop gain
(usually represented as AV or AOL). Typically AOL~106
– This causes instability: the open-loop output saturates
– Closed-loop circuits can stabilize the OpAmp, allowing linear
applications (such as amplifiers) to be implemented
• To improve stability, an internal capacitor is often added in
the design of the OpAmp (inserting a pole at s = -wCol)
– Open-loop cut-off frequency wCol is chosen in the order of 10 rad/s
– This overwhelms the effect of any internal parasitic capacitances. It’s
said to be an internally compensated OpAmp. Most OpAmps are!
 this is a DC model
Frequency model for an
internally compensated
OpAmp

14. 14 Signals and electronic systems design
M Mata
OpAmp Open-loop frequency response
Typical open-loop response of a compensated amplifier
 The constant -20dB/dec rate of change of gain with
frequency implies that there is only one dominant pole
(the internal compensation capacitor)
 Having a single dominant pole makes
it always stable in closed-loop
AOL(dB)
Open-loop
critical frequency
fCol fT
Midrange
f (Hz)
106
0
~10Hz
1Hz ~1MHz
-20dB/dec
Open-loop unity-gain frequency
 The frequency at which the
OpAmp shows unity open-
loop gain AOL=1, fT, is a
relevant parameter

15. 15 Signals and electronic systems design
M Mata
VO
VIN
OpAmp closed-loop bandwidth. GBP
• Example: non-inverting amplifier
• Closed-loop gain is
• Closed-loop cut-off frequency is:
• Both wCol and AOL are internal design parameters of the OpAmp. The
product wColAOL is a constant, usually named GBP or GBWP (gain-
bandwidth product). Typ. GBP ~ 1MHz to 10MHz
• Closed-loop bandwidth wCL is then given by:
 = feedback ratio
𝑉 𝑠 = 𝐴
𝑉 𝑠 − 𝑉 𝑠 𝛽
𝑠/𝜔 + 1
𝑉 𝑠 𝑠/𝜔 + 1 = 𝐴 𝑉 𝑠 − 𝑉 𝑠 𝛽
𝑉 𝑠 𝑠/𝜔 + 1 + 𝐴 𝛽 = 𝐴 𝑉 𝑠
As AOL>>1:
wCL
ACL
𝑪𝑳
𝑪𝒐𝒍 𝑶𝑳
𝑪𝑳 𝑪𝑳

16. 16 Signals and electronic systems design
M Mata
OpAmp closed-loop bandwidth. GBP, fT
For open-loop response curves with -20dB/dec roll-off
(compensated OpAmps), the closed-loop -3dB bandwidth limit
(cut-off frequency wCL) occurs at the ACL intercept with the
open-loop gain curve
AOL
fCol
fT
fCL
ACL=100
Open-loop cut-off
frequency
-20dB/dec
-3dB
𝑪𝑳 𝑪𝑳 𝑪𝒐𝒍 𝑶𝑳
Datasheets show either GBP
(gain bandwidth product) or fT
(unity gain bandwidth)
fT = Open-loop Unity-gain frequency
Then the open-loop unity-gain frequency fT
is coincident with the GBP value:
aka Unity-gain bandwidth
ACL=10
ACL=1

17. 17 Signals and electronic systems design
M Mata
OpAmp closed-loop bandwidth. GBP
A certain compensated op-amp has an open-loop gain AOL=106
and a unity gain bandwidth fT=2MHz. For the following
situations, discuss whether this gain can be sustained at a
signal frequency of 300kHz. If not, suggest what value of unity-
gain bandwidth the op-amp should have.
a) Non-inverting amp. having a DC closed-loop gain ACL=10.
b) Inverting amplifier having a DC closed-loop gain ACL= -10.
• For inverting stages, the BW is calculated from the GBP
assuming the NON-INVERTING gain (aka NOISE gain).
• Example:

18. 18 Signals and electronic systems design
M Mata
Example popular Op-amps
Parameter
LM741 LF411
AOL
fT
SR
Zin(OL)
Zout(OL)
Voff
IB
Ioff
(Bipolar) (FET)
2 x 105
1.5MHz
0.5V/ms
2MW
75W
1.0mV
80nA
20nA
2 x 105
4.0MHz
15V/ms
1012 W
75W
0.8mV
50pA
25pA
DC open-loop gain
Unity-gain bandwidth
Output offset voltage (at V+=V-)
Open-loop input impedance
Open-loop output impedance
Input bias current IB=(i++i-)/2
Input offset current Ioff =|i+-i-|
Slew rate
CMRR 95dB 100dB
Common-mode rejection ratio

19. 19 Signals and electronic systems design
M Mata
Dynamic Performance of Amplifiers
• The Slew Rate models some limitations for dynamic signals
in time domain (specially relevant for square signals)
• The GBP models these limitations in frequency domain
• In a wider context, no real amplifier has equal gain at all
frequencies, and will exhibit a tail-off in performance both at
high and low frequencies
• This non-ideal behavior is a result of:
- Limitations of the active devices in the circuit (i.e.
OpAmps)
- Series and shunt capacitances in the circuit, added to
achieve the required operation
- Parasitic impedances due to wiring and traces in the
circuit layout: how components are arranged and
interconnected in the printed circuit board (PCB)

20. 20 Signals and electronic systems design
M Mata
Effect of capacitive coupling
• When input signals contain an unwanted DC component, it
is usually blocked by using a series coupling capacitor
 It blocks the DC component of the signal while letting higher
frequencies through
• As a side effect, this also leads to a drop of gain at lower
frequencies (as the series C behaves as a high-pass filter):
C
R
Vin
Vo
C
C
s
s
s
H
w
w


1
)
(
RC
C
1

w
C
w C
w
Phase lead

21. 21 Signals and electronic systems design
M Mata
Effect of parasitic series L / shunt C
• Stray wiring or parasitic capacitances and inductances are
often integral to the components, or to how they are wired
on a PCB
• As a side effect, this causes the gain of the amplifier to drop
at high frequencies (as the series L and/or shunt C behaves
as a low-pass filter):
R
Vin
C
Vo
C
s
s
H
w


1
1
)
(
RC
C
1

w
C
w C
w
Phase lag

22. 22 Signals and electronic systems design
M Mata
Combined effect: band-pass behaviour
fL fH
Lower cut-off
frequency
Upper cut-off
frequency
Phase lead Phase lag
Bandwidth (BW)
Intended operation
ACL=

23. 23 Signals and electronic systems design
M Mata
t90
t10
tr
90%
10%
100%
Pulse / square signal response
The described effects may end up producing a poor amplifier
response to a pulsed input:
High freq
Low freq (~DC) Low freq (~DC)
Rise time
High freq
Many parasitic poles  may show
oscillations (if underdamped)
vi(t)
t
Slew rate
Limited by slew rate and bandwidth BW: 𝒓

24. 24 Signals and electronic systems design
M Mata
Avoiding linear distortion in amplification
 constant gain over the range
of frequencies contained in
the input signal
To avoid linear waveform distortion, an amplifier should have:
f
f
 A phase delay that is always
0 (usually not feasible), or
linear versus frequency
 Then all frequency components
will be delayed by the same
amount of time:
All frequency components delayed by the same time k
0º

25. 25 Signals and electronic systems design
M Mata
Non-linear Distortion: saturation
• Any amplifier’s output voltage range (output voltage swing) is
limited by its supply voltages +VCC and –VCC:
• vOmax < +VCC
• vOmin > -VCC
• If vO = ACLvin exceeds these
limits, saturation (clipping)
occurs
 this is a non-linear distortion
vOmax
vOmin
vi
vO
slope = ACL
• Any DC component in the
input makes clipping more
likely to occur, as the DC
offset is also amplified

26. 26 Signals and electronic systems design
M Mata
Measuring distortion
• The Total Harmonic Distortion (THD) is a frequency-based
measure of how much distortion is introduced by these
undesirable effects
Fundamental harmonic Harmonic distortion components

27. 27 Signals and electronic systems design
M Mata
Total Harmonic Distortion
• THD is defined as the amplitude ratio of the geometric
average of all harmonic distortion terms to the
fundamental harmonic:
• A well-designed audio amplifier might have a THD of about
0.01% at rated power output
%
100
.....
2
4
2
3
2
2





f
V
f
V
f
V
f
V
THD
Vf is amplitude of fundamental frequency
V2f is amplitude of second harmonic
Vnf is amplitude of nth harmonic
• Harmonic amplitudes Vnf can be analytically calculated
using the Fourier transform, or measured using a spectrum
analyser
 It is a digital instrument that digitizes the signal with a very high
sampling ratio, then calculates its FFT (Fast Fourier Transform)

28. 28 Signals and electronic systems design
M Mata
Total Harmonic Distortion
Example: Calculate the THD of an audio power amplifier
driving an 8W load from the following measurements using a
1kHz test signal. The measured rms voltage of the 1kHz signal
at the load is 2.826V.
THD 
V
2 f
2 V
3f
2 V
4 f
2 .....
V
f
100%
THD 
0.01132
0.06332
0.00142
.....
2.8258
100%
THD  2.38%
Harmonic Voltage (Vrms)
2
3
4
5
6
7
8
9
0.0113
0.0633
0.0014
0.02
0.0005
0.0005
0.0003
0.0006

29. 29 Signals and electronic systems design
M Mata
Stability: Gain and Phase Margin
o
V
+
-
AOL(f)
Vin
Vo

Instability sets in if, at any given frequency,
it may happen that 1 + AOL(f) = 0
Single dominant pole systems can only
reach a phase of -90º  always stable
That’s why most OpAmps are internally
compensated this way
Open-loop gain depends on frequency: AOL=AOL(f)
𝟐𝟎 𝐥𝐨𝐠 𝜷𝑨𝑶𝑳 𝒇 𝒅𝑩
𝑶
𝒊𝒏
𝑶𝑳
𝑶𝑳
Gain margin and phase margin measure
stability (how far from the above condition)
Phase margin
Gain
margin
occurring at the same frequency

30. 30 Signals and electronic systems design
M Mata
Stability Criteria
Gain(dB)
fC1 fT
f (Hz)
fC2 fC3
AOL(mid f)
-20dB/dec
-40dB/dec
-60dB/dec
• If the closed-loop gain ACL= intersects
the open-loop response on a -40db/dec
or greater region (across more than 1
dominant pole), instability can occur as
phase may be -180º for |AOL(f)| = 1
However multiple-pole systems can reach a phase of -180º or more (-90nº for n
poles)  may be unstable!. For instance, for an uncompensated OpAmp:
1st pole
2nd
pole
3rd
pole
-90º
phase
-180º
phase
-270º
phase
• To ensure stability, any
OpAmp must be operated
at a closed-loop gain ACL
such that the roll-off rate at
the corresponding BW
does not exceed -20dB/dec
(fC2 in the example)
BW
ACL
fC1, fC2, fC3, … internal parasitic poles

31. 31 Signals and electronic systems design
M Mata
Phase compensation
AOL
fT
f (Hz)
AOL(mid f) Uncompensated open-loop gain
(showing 3-poles behaviour)
Effect of phase compensation on OpAmp response
With some compensation
BW1
ACL
With more compensation
(2-poles behaviour)
BW2
Inserting one additional dominant pole (external capacitor) makes
the system approach the single-pole behaviour (-20dB/dec)
-20dB/dec
-60dB/dec
Gain (dB)
-40dB/dec
With no (or too little)
compensation,
operating at ACL the
bandwidth is BW1.
Phase can reach -180º
(2-pole gain roll-off) 
instable
Adding enough
compensation the
bandwidth decreases to
BW2. But now phase is
under -180º  stable

32. 32 Signals and electronic systems design
M Mata
Phase Compensation example
LM101A uncompensated OpAmp
IC pins 1, 8:
compensation terminals
C1: external compensation capacitor
AOL (dB) AOL (dB)
ACL
Uncompensated
C1=3 pF
C1=30 pF

33. 33 Signals and electronic systems design
M Mata
Driving Capacitive Loads
• Amplifier load capacitance is a potential problem
- A capacitive load CL inserts an additional pole at s = -ROCL, decreasing phase
margin (increasing overall phase lag, potentially over -180º)
• ZL can be parasitic: PCB capacitance can build up quickly
- For instance on a typical 0.03” G10 dielectric 2-sided PCB, a 0.025” trace
running over a ground plane will create a capacitance of about 22pF/foot
• Even a relatively small load capacitance (i.e., <100 pF) can be
troublesome at frequencies near the BW limit; even if not causing
outright oscillation, it can still stretch amplifier settling time

34. 34 Signals and electronic systems design
M Mata
External Compensation – Series Resistor
• At high frequencies, CL is dominant over any load resistance RL:
• Then RSERIES keeps the OpAmp output resistance and feedback
network separated from the capacitive load ZL
• Usually RSERIES values from 5Ω to 15Ω are sufficient
SERIES RESISTOR COMPENSATION TO STABILIZE AN OPAMP DRIVING
CAPACITIVE LOADS
ZL=ZCL||RL
𝑺𝑬𝑹𝑰𝑬𝑺 𝑪𝑳 𝑳 𝑺𝑬𝑹𝑰𝑬𝑺
𝑳
𝑳 𝑳
𝝎→
𝑺𝑬𝑹𝑰𝑬𝑺
𝑳
𝑳 𝑳
𝑺𝑬𝑹𝑰𝑬𝑺
𝑳