CRC, Cyclic Redundancy Check. Error coding technique

1. Cyclic Code redundancy
CRC

2. CRC Introduction
• CRC is technique used in the communication system to add some error
check bits at the Transmitter side using Encoder circuits and check the
message data for error free transmission at the Receiver side using the
decoder circuit.
• In this method of CRC error checksum we add some CRC checksum bits at
the transmitter side using the encoder and then send the message data
including CRC bits to the Receiver and then decode the data which
received at the receiver using the same CRC method.
• Now if the CRC checksum bits are zero at the receiver side it means there
is no error else there occur some error at the transmission medium. Due
to that the message has not properly received.
• The CRC Encoder/Decoder circuit can be design using the help of LFSR. The
LFSR generate the CRC bit using the feedback XOR gates.

3. Explanation of CRC
• Take a message data which is going to transmit over the medium.
• Now generate the message polynomial M(x) using the data bit as the increasing
order of the power of x.
• Take the predefined CRC polynomial C(x) as a polynomial of x.
• Then take the highest degree term of x from the CRC polynomial C(x) as xi.
• Multiply the message polynomial M(x) by the xi CRC highest degree term of CRC polynomial.
• Then divide the product of xi . M(x) by the CRC polynomial C(x). And take the remainder data
as a polynomial of x as R(x).
• Convert the remainder polynomial R(x) to the corresponding binary bits where the respective
power coefficient of x occur as 1 and other as 0.
• Append the CRC bits to the message data to the transmit the data over the medium.
• Now at the receiver side the same CRC checksum circuit is used to decoding the data by
passing the data over the decoder circuit in the same process as encoding.
• Now again check the remainder data. If it is a polynomial of x as zero coefficient of each x
term. It means there is no error else if it is a polynomial of non zero coefficient of x means
there is a error in the transmitted data.

4. CRC Example
Take a example CRC – 3 checksum polynomial as x3 + x2 +1.
Now let the message data is 8 bit binary value 10101010.
Generate the message polynomial as the following
M(x) = 1 * x7 + 0 * x6+ 1 * x5 + 0 * x4 + 1 * x3 + 0 * x2 + 1 * x1 + 0* x0
M(x) = x7 + x5 + x3 + x1
The message polynomial is generated in the increasing order of x starting with x0.
Now multiply the message polynomial by the highest degree of CRC polinomial of x2.
G (x) = x3 * ( x7 + x5 + x3 + x1 )
G (x) = x10 + x8 + x6 + x4
divide the G (x) by the CRC polynomial C (x) and take the remainder and quotient.
M (X) = C (x) * Q (x) + R(x) : where R (x) is the remainder.
: Q(x) is the quotient of G (x ) / C(x)

5. Division by CRC
x7 + x6 + x4 + x3 + x2 + x
x3 + x2 + 1 ) x10 + x8 + x6 + x4 (
x10 + x9 + x7
x9 + x8 + x7 + x6 + x4
x9 + x8 + x6
x7 + x4
x7 + x6 + x4
x6
x6 + x5 + x3
x5 + x3
x5 + x4 + x2
x4 + x3 + x2
x4 + x3 + x
x2 + x

6. Result
Of CRC
• The result of CRC is 110.
• Now the encoder output data is { message data : CRC bits}
• {10101010 : 110}
• This data will go to the decoder block to check the error on the message
data.
• If the CRC decoder bits are zero then it means there is no error.
• Repeat the same encoder process to the decoder and get the CRC data
bits.

7. CRC generation using Verilog Design
• The data is a serial data form as sin to the Encoder circuit and having a data valid
signal at the same time and having a start signal at one clock cycle early.
• CRC can be generated using Encoder Circuit which consist a LFSR register.
• The Encoder circuit CRC encoder send data and CRC data to output as
data_crc_out and data_crc_valid signals.
• To the CRC decoder circuit which has the input data_crc_out and data_crc_valid
and start bit is functioning same as the encoder circuit and checking the error on
sent data if there is any error then it makes HIGH the ERROR signal else it is LOW.
• As the ENCODER/DECODER circuit is same so there is one more signal E_D_en
which triggering the circuit to function either Encoder or Decoder.
• The LFSR register block consist of a number of FF as the CRC bits.
• So as the LFSR circuit having FF so there are two more signal as clk and reset.

8. Block diagram for CRC
Encoder/ Decoder
Top Level Black box for CRC
clk clk
Data_Crc_out
Data_Crc_out
Data_Crc_valid Data_Crc_valid
Test
cr DECODER
ENCODER EN_en
DC_en
Bench
Sin
ERROR
Data_valid
rst rst

9. CRC- 3 ENCODER / DECODER BLOCK
DIAGRAM
start
clk Data_Crc_out
rst Data_Crc_valid
sin
Data_valid
ERROR
E_D_en

10. Block diagram of LFSR
• LFSR is used to create the CRC checksum bits.
• The block diagram for a an example x3 + x2 +1.

11. Verilog code for CRC -3

12. Timing diagram for Data 10101010
for Encoder Decoder

13. Result
• Hence I have verified all the operation on a CRC ENCODER/DECODER
Circuit.
• Now it’s your time to do some CRC Checksum data calculation using some
more example as the same method.
Thankyou