2. Blocks of a Microprocessor
A separate wire
is required for
each bit in each
register
Impractical to do
this at design &
development
stages
2Source: www.transtutors.com/homework-help/computer-
science/computer-architecture/cpu/general-register-organization/
3. Blocks of a Microprocessor
3
Literal
Address
Operation
Program
Memory
Instruction
Register
STACK Program Counter
Instruction
Decoder
Timing, Control and Register selection
Accumulator
RAM &
Data
Registers
ALU
IO
IO
FLAG &
Special
Function
Registers
Clock
Reset
Interrupts
Program Execution Section Register Processing Section
Set up
Set up
Modify
Address
Internal data bus
Source: Makis Malliris & Sabir Ghauri, UWE
4. Bus
Common electric path between multiple units
Collection of wires, 1 wire for each bit
Interconnect registers & other I/O units
Only 1 register/unit can occupy the bus at a time
1-to-1 or transfer
1-to-many transfer
4
5. Bus Selection
Select an input among multiple inputs
Using multiplexers
Using tri-state buffers
5
6. Bus Selection Using Multiplexers
6
Source: www.ee.oulu.fi/research/tklab/courses/521415A/exercises/nexercise3a.html
4 wires instead of 16
7. Tri-State Buffer
Use 3 state gates
High impedance
Open circuit
7
Enable In Out
0 0 High impedance
0 1 High impedance
1 0 0
1 1 1
8. Bus Selection Using Tri-State Buffers
8
Source: www.electronics-tutorials.ws/logic/logic_9.html
9. Types of Busses
Data bus
Instruction bus
Control bus
Address bus
Memory bus
I/O bus
These can be internal/external to CPU
9
10. Bus Protocols
IBM PC (PC/XT)
Industry Standard Architecture (ISA)
Peripheral Component Interconnect (PCI)
PCI Express (PCI-E or PCIe)
Accelerated Graphics Port (AGP)
Universal Serial Bus (USB)
10
11. What’s Defined by Bus Protocol?
Bus width
USB 2-bit, PIC instruction bus 14-bit, PCI 32-bit, PCIe
64-bit
Speed
PCI 33 MHz, PCIe 133 MHz
Bandwidth
PCI 133 MB/S, PCIe 4 GB/S, USB 3.0 500 MB/s
Who can communicate & when
Master
e.g., CPU
Slave
e.g., memory 11
12. Serial vs. Parallel Busses
Which has high throughput?
Parallel I/O
Expense & inconvenience of long/parallel lines
Parallel I/O maximum distance ~2m
Cable capacitance limits unbuffered data transfers
More wires, drivers, receivers
Relatively simple circuits
Serial I/O
Fast speeds over long distances
Less wires, less space, less costly
Relatively more complex circuits 12