Updated Resume.

1. DIVYAM VIRMANI
Email: Divyam.virmani@gmail.com
Contact: 9908863716, 9871323315
Career Objective
To work in a stimulating work environment where I can take up new challenges and through the laid
forth challenge I can learn and prosper.
Summary
• 2+ year working experience in Product validation.
• Part of 1 complete tapeout and currently pre Si validation (emulation) phase.
• Been part of emulation and porting activity of FPGA.
• Developed various in-house automated tools in Tcl/Perl.
• Developed test benches for IC both in validation and emulation activity.
• Has experience working in lab with use of CROs, function generators etc.
• Has experience working with traffic generators like Ixia, Smartbits, Spirent.
• Has experience in creating and editing ARM based firmware.
• Has experience working with Xilinx Vivado and ISE tools. (chipscopePro, Coregen)
• Has experience using debuggers like IAR.
• Has experience working on IEEE 1149.1 and 1149.6 JTAG and AC-JTAG STDs.
• Has experience knowledge of Ethernet IEEE802.3, MAC and physical layer protocols.
• Has working knowledge of version control tools like svn, cvs etc.
Professional Experience
• Currently working as System Validation Engineer in Microsemi Corporation from June2015
• Worked as Validation Engineer in Vitesse Semiconductors (now Microsemi) from July 2014 –
June 2015
• Worked as Validation Engineer intern in Vitesse Semiconductor from Jan 2014 to July 2015.
Skill Set
Languages: Verilog
Script Languages: Perl, Tcl, Bash
Tools: Xilinx Vivado, ISE, ChipscopePro, Coregen. Microsemi Libero, FlashPro.
IDE: Audrino, Cadence Virtuoso
Protocols/STDs: JTAG IEEE 1149.1, 1149.6, Ethernet Layer1 IEEE802.3
Lab Instruments: CROs, DSAs, Ixia, SMB, Spirent.
Microsemi SOC – June 15 to Current
1. PORTING Automation
AIM: Reduce time and manual intervention required to convert ASIC RTL to on FPGA emutable
RTL.
Wrote PERL script that will enable user to download a new ASIC RTL available on svn and convert
it to FPGA usable RTL so that the whole team can further use the ported RTL and test it.
Earlier process used 1 complete day(or more), reduce to 1hr job with no human intervention.
Script made was modular and was divided in functions as-
a. Download ASIC RTL
b. Download already ported FPGA RTL

2. c. Compare in TOP file changes
d. Compare simulation file changes
e. Compare synthesis file changes
f. Edit Clocking instances
2. PROGRAMING Automation
AIM: To remove manual intervention to generate a programming file for Microsemi’s FPGA with
specific configurations.
Wrote PERL script which allows the user to generate a configuration file that is used by internal
Microsemi tool to generate a programming file. The PERL script requires particular set of inputs and
configurations.
Earlier process used 0.5 hour manually to generate 1 particular programming file while the process
was reduced to 30-40 seconds.
3. Emulation Use Models
AIM: To write use models to test various chip functionalities and security features.
Read the specifications provided by designers and formulated the use models and use cases and
gave review. Following Use Models were covered by me-
1. Low Power mode.
2. Only Fabric on mode.
3. Security features.
4. ARM based features.
5. Device initialization features.
Review of above tests still in process.
Vitesse Semiconductor – July 14 to May 15
1. Functional Validation Of 10G Physical Layer Chip
AIM: To validate following list of Features of 10G PHY:
• GPIO Functionality
• Loopbacks
• Stress Tests
• Clock Output Tests
• Squelch Tests
• Low Power Mode Tests
• BIST test
Test cases were written in Tcl and automated to require least human intervention.
2. Development/Automation of GPIB Library
AIM: To develop GPIB library to automate testing which requires CRO/analysers/Power switching.
Wrote Tcl scripts and created routines that will able to control GPIB available devices using our
environment and our commands. Done first time in Vitesse SC India lab, got appreciation from
IDC head.
3. Development of Unified Validation Environment
AIM: To create a new infrastructure for regressions similar to UVM for validation.
I worked to edit parser written in C and Tcl to generate register mapping file in tcl from XML file. I
wrote as well as edited functions for DUT read/write and tester initialization and fire up. I worked
to create and implement regression system for validation.
4. Board Design for Validation
I worked to design the validation characterization board in house rather than transporting from
other sites. I acted as lead of team of size 3 and worked on open source tool from fedora to
develop Arduino board. Layout is still in progress.

3. Academic Details
Course Board/University
Year of
passing
Percentage/C
GPA
MTech VLSI and
Computer Engineering
International Institute of Information
and Technology Hyderabad
2014 8.96
BTech ECE GGSIPU 2012 80.1
H.S.C. CBSE 2008 92(PCM)
S.S.C. CBSE 2006 91.4
Academic Projects
1. Implementation of Micropipeline on FPGA Sep-Dec 2013
o Since Asynchronous clocking techniques are power efficient aim was to develop asynch pipeline
o Languages/Tools- Verilog , Quartus
2. Sudoku May 2013
o Course project did it in Python
o Languages Used- Python
3. Hardware implementation Image Segmentation Oct-Nov 2012
o Aim was to differentiate between background and foreground of image using hardware.
o Languages/Tools used- VHDL, ModelSim
4. Domino Logic with variable threshold Voltage Keeper May 2013
o Project was part of Course project, aimed to decrease power, delay and increase Noise Margin
in regular Domino Logic circuits.
o Tool Used – Cadence Virtuoso
5. Farm and Cold Storage Monitor and Control System Sept-Nov 2011 &
Jan-March 2013
o Aim was to collect data from various sensors installed at different place in agriculture field and
send the details to remote user using GSM, ZigBee.
o Languages/Tools used- Arduino, Python, XCTU
6. A Low-Cost LIDAR Technology based on Infrared Detection March-May 2012
o Like RADAR, we wanted to implement same technology for low range application so we used
Light Sensor hence name LIDAR. Sense & kill feature prepared.
o Languages/Tools used- Arduino, Processing
Internship
1. Vitesse SemiConductor, Hyderabad AP Jan-Jun 2014
o Working for Unified Validation Environment as Validation Intern
2. Summer Intern, Bharat Electronics Limited, Gaziabad, U.P. June-July 2011
o Worked on radar component (IFF) Identification of friend & Foe, which is used to distinguish
enemy planes & native country planes.
3. Embedded Systems Training, Prolific Technologies Pvt Ltd. June-July 2010
o Learnt about hardware and software implementation for Embedded Systems, particularly based
on 8051 Microcontroller
4. Summer Project Intern, Uurmi Systems Hyderabad June-July 2013
o Project was to implement cheap LIDAR based ditch detection machine. Had hands on
experience with IMU and laser sensors.
o Tools Used- Arduino IDE.

4. Extra Curriculum
1. Head PRMedia Team College Fest 2011
2. IEEE Student Branch Program Head 2009-2012
o Conducted seminars on Matlab, Robotics etc
3. Conducted Robowars Event in college fest
Achievements
1. Got recognition in Vitesse Semiconductor Industry, as spot award for working exceptionally well in
my first validation project.
2. Intra College Soccer Runner up
3. Major Project “LiDAR” got Second Price at University Level
4. Qualified GATE 2012 with 99.08 percentile.
5. Represented own school and Participated in ‘Perfect Programmers’ in inter school competition
6. Got 9 Pointer in Advance Programming System (C/C++).
(DIVYAM VIRMANI)