The System Designer's Guide to VHDL-AMS 2002, Chapter 18. Case Study 3: DC-DC Power Converter

1. Abeer Fathy Sayed
Aya Mahmoud Ibrahim
Rawan Ramzy Sayed
Sara Abd-ElLateef

2. DC-DC switching power supply
• For the RC airplane system, a stepdown converter is required
to convert the 42 v used to power the propeller motor to the
4.8 v needed for the on-board servo electronics.

4. There are two basic types of PWM switching regulators:
forward mode and flyback mode.
From these two basic modes, the common topologies are
formed.
We will use the buck(step-down) converter which is a forward
mode converter.
Voltage-Mode Control

5. The converters have four basic elements:
 power switch for creating the PWM control waveform,
 diode,
 inductor and a capacitor.

6. The Requirements of our Regulator Design

7.  The buck converter has two basic modes of operation:
Continuous mode: current is always flowing through L1
whether the switch (SWl) is on or off
Discontinuous mode: the inductor current goes to zero
during part of the off time of SWl.
The converter is designed to operate only in the continuous
mode by sizing the inductor according to the worst-case load
conditions to avoid the zero current threshold. Keeping the
buck converter operating in continuous mode also simplifies
the design and analysis considerably.

8. During the circuit on state, SWl is on, D1 is reversed biased (off) and current
passes through the inductor to the load.
 During the circuit off state, SW1 is off, and D1 is forward biased (on),
maintaining the forward current through L1.
Continuous mode

9. The amount of energy transferred to the load is controlled by the
duty cycle of the switch control waveform.
The duty cycle can range from 0.0 to 1.0, but typically falls
between 0.05 and 0.95 (5% to 95%).
D=
𝑇𝑜𝑛
𝑇𝑠
Ton = D x Ts
Toff = (1 – D) x Ts

10.  Shows some representative waveforms for the buck converter
operating in continuous mode at steady state with a duty cycle of
about 30%.

11. Vout = Vin x D
Vout = (Vin x D) – Vd
D=
𝑽𝒐𝒖𝒕+𝑽𝒅
𝑽𝒊𝒏
=
𝟒.𝟖+𝟎.𝟕
𝟒𝟐
= 0.131
Ton = D x Ts
Toff = (1-D) x Ts
Select Duty Cycle

12.  The goal is to select a minimum value for L1 such that the
converter operates in continuous mode.
VL= 𝐿 𝑥
Δ𝐼𝐿
Δ 𝑡
Lmin =VL 𝑥
Δ 𝑡
Δ𝐼𝐿(𝑚𝑎𝑥)
= (Vin - Vout) x
Ton
Δ𝐼𝐿(𝑚𝑎𝑥)
= (42-4.8) x
5.2
30
= 6.5 mH
Calculate the values (L1)

13. Cmin =
Δ𝐼𝑜𝑢𝑡
8 x Fs x Δ 𝑉𝑜𝑢𝑡
=
30 mA
8 x 25 HZ x 100 mV = 1.5 mF
Rload(min) =
𝑉𝑜𝑢𝑡
Iout(max)
=
4.8 𝑉
2 A
= 2.4 ohm
Rload(max) =
Vout
Iout(min)
=
4.8 𝑉
15 mA
=320 ohm
Calculate the values (L1)

14. Structural VHDL-AMS code for a buck converter
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity tb_BuckConverter is
port ( ctrl : std_logic);
end tb_BuckConverter;

15. architecture tb_BuckConverter of tb_BuckConverter is
terminal vin : electrical;
terminal vmid : electrical;
terminal vout : electrical;
begin
L1:entity work.inductor(ideal)
generic map(ind => 6.5e-3)
port map (p1 => vmid, p2 => vout);
C1:entity work.inductor(ideal)
generic map(cap => 1.5e-6)
port map (p1 => vout , p2 => electrical_ref);

16. VinDC:entity work.v_constant(ideal)
generic map(level => 42.0)
port map (pos => vin, neg => electrical_ref);
RLoad:entity work.inductor(ideal)
generic map(res => 2.4)
port map (p1 => vout , p2 => electrical_ref);
D1:entity work.diode(ideal)
port map (p => electrical_ref , n => vmid);
sw1:entity work.switch_dig(ideal)
port map (sw_state => ctrl , p2 => vmid , p1 => vin);
end architecture tb_BuckConverter;

17. Capacitor Model
For switching power supplies it is often necessary to consider the effect
of the equivalent series resistance (ESR). If the ESR is too large, it can
introduce an unwanted "zero" in the frequency response, which may
lead to instability.
In this model, the capacitor uses the user specified initial voltage v_ic,
provided the value is other than real'low. This value is the default value
for the generic constant and is used to determine whether initialization
is required.

18. Modeling with VHDL-AMS
library ieee; use ieee.std_logic_1164.all;
entity capacitor is
generic (cap : capacitance;
r_esr : voltage := 0.0;
v_ic : voltage := real'low);
port ( terminal p1 , p2 : electrical);
end entity capacitor;

19. architecture esr of capacitor is
quantity v across i through p1 to p2;
quantity vc : voltage; --internal voltage across capacitor
begin
if domain=quiescent_domain and v_ic/=real'low use
vc == v_ic;
I == 0.0;
else
vc == v-(I * r_esr);
I == cap*vc'dot;
end use;
end architecture;

20. Digitally controlled ideal switch model.
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity switch_dig is
generic (r_open : resistance := 1.0e6;
r_closed : resistance := 1.0e-3;
trans_time : real := 1.0e-9);
port( sw_state : in std_logic;
terminal p1 , p2 : electrical);
end entity switch_dig;

21. architecture linear of switch_dig is
signal r_sig : resistance := r_open;
quantity v across i through p1 to p2;
quantity r : resistance;
begin
--detect switch state and assign resistance value to r_sig
DetectState : process (sw_state)
begin
if ( sw_state'event and sw_state = '0')then
r_sig <= r_open;
elsif (sw_state'event and sw_state = '1')then
r_sig <= r_closed;
end if;

22. end process DetectState;
r == r_sig'ramp ( trans_time , trans_time );
v == r * i;
end architecture linear;

23.  The output voltage of the buck regulator is a function of
the input voltage and the duty cycle of the switching
waveform.
 We can adjust the output voltage simply by changing the
duty cycle.
 Pulse-width modulation (PWM) control techniques provide
an effective way of doing this.
 The simplest method for controlling the output voltage
level in PWM switching regulators is voltage-mode control.
Voltage-Mode Control

24. In order to do this we need to modify the basic buck
converter to provide a voltage control input.

25.  Examining the simulation, we see that a control voltage of 0.327 V
provides a PWM waveform, sw_ctrl, with the desired duty cycle of 13.1% .

26.  Using the following equation with the duty cycle (D) replaced by the
ratio (
𝑉𝑐
𝑉𝑟𝑎𝑚𝑝
):
𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛 ×
𝑉𝑐
𝑉𝑟𝑎𝑚𝑝
− 𝑉𝑑
 By setting 𝑉𝑟𝑎𝑚𝑝 to 2.5 𝑉 and solving for 𝑉:
𝑉𝑐 = 𝑉𝑟𝑎𝑚𝑝 ×
𝑉𝑜𝑢𝑡 + 𝑉𝑑
𝑉𝑖𝑛
= 2.5 ×
4.8 + 0.7
42
= 0.327

27. We can replace the switching elements in the switched power supply with a
state-averaged model, producing a smooth (averaged) voltage on the output.
By replacing the simulation-intensive switching model :
The simulation times are significantly reduced.
An averaged model allows us to run a small-signal frequency (AC) analysis
and examine the stability of the control loop.
An averaged model allows us to run a closed-loop time domain analysis
and examine how the system responds to sudden changes in load or line
conditions.
Averaged Model

28. library ieee_proposed;
use ieee_proposed.electrical_systems.all;
entity buck_sw is
generic (Vd : voltage := 0.7; --diode voltage
Vramp : voltage := 2.5 );
port ( terminal input, output, ref, ctrl: electrical );
end entity buck_sw;
Averaged Model

29. architecture average of buck_sw is
quantity Vout across lout through output to ref;
quantity Vin across input to ref;
quantity Vctrl across ctrl to ref;
begin
Vout = Vctrl * Vin / Vramp-Vd;
end architecture average;
Averaged Model

30. The averaged waveforms are a “smooth” approximation of the
original waveforms.

31.  Input voltage variations or output load changes cause the
output voltage to vary outside of the specified limits.
 So we need a feedback mechanism that senses a change in
the output voltage and adjusts the duty cycle to bring the
voltage back to the desired level.
Closing the Loop

33. Loop Control
library ieee_proposed;
use ieee_proposed.electrical_systems.all;
entity sw_LoopCtrl is
generic ( r_open: resistance := 1.0e6;
r_closed: resistance := 1.0e-3;
sw_state: integer range 1 to 2 := 1 );
port ( terminal c, p1, p2 : electrical );
end entity sw_LoopCtrl;

34. Loop Control
sw2 : if sw_state = 2 generate
r1 = r_open ;
r2 = r_closed;
end generate sw2;
v1 = r1 * i1;
v2 = r2 * i2;
end architecture ideal;
architecture ideal of sw_LoopCtrl is
quantity v1 across i1 through c to p1;
quantity v2 across i2 through c to p2;
quantity r1, r2 :resistance;
begin
swl: if sw_state = 1 generate
r1 = r_closed;
r2 = r_open ;
end generate swl;

35. Transfer function

36. Transfer Function
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity comp_2p2z is
generic ( gain : real := 100.0; - - high DC gain for good load regulation
fp1 : real := 7.5e3; --pole location to achieve crossover frequency
fp2 : real := 531.0e3; - - pole location to cancel effect of ESR
fz1 : real := 403.0; - - z e r o locations to cancel L-C filter poles
fz2 : real := 403.0 );
port ( terminal input, output, ref: electrical );
end entity comp_2p2z;

37. Transfer Function
architecture Itf of comp_2p2z is
quantity vin across input to ref;
quantity vout across lout through output to ref;
constant wp1:real := math 2 pi * fp1; - - Pole freq (in radians)
constant wp2:real := math 2 pi * fp2;
constant wz1:real = math_2_pi * fz1; --Zero freq (in radians)
constant wz2:real := math 2 pi * fz2;

38. constant num : real_vector := ( 1.0, (wz1 + wz2) / (wz1 * wz2), 1.0 / (wz1 *
wz2));
constant den : real_vector := ( 1.0e-9, 1.0, (wp1 + wp2) / (wp1 * wp2),
1.0 / (wp1 * wp2) );
begin
vout = = - 1 . 0 * gain * vin'ltf ( num , den );
end architecture Itf;
Transfer Function

39. Load Regulation

40. Load Regulation
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity pwl_load is
generic ( load_enable : boolean := true;
res_init : resistance;
res1 :resistance;
t1 :time;
res2: resistance;
t2 :time );
port ( terminal p1, p2 : electrical );
end entity pwl_load;

41. Load Regulation
architecture ideal of pwl_load is
quantity v across i through p1 to p2;
signal res_signal: resistance := res_init;
begin
load_present'if load_enable generate
if domain = quiescent_domain or domain = frequency_domain use
v = i * res_init;
else
v = i* res_signal'ramp(1.0e-6, 1.0e-6);
end use;

42. Load Regulation
create_event : process is
begin
wait for t1;
res_signal <= res1;
wait for t2 – t1;
res_signal <= res2;
wait;
end process create_event;
end generate load_present;
load_absent : if not load_enable generate i= 0.0;
end generate load_absent;
end architecture ideal;

43. Line Regulation

44. Design Trade-Off Study
The results verify the inverse relationship between Lmin,Cmin
and the clock switching frequency

45. Design Trade-Off Study

46. Design Trade-Off Study

47. Design Trade-Off Study