Implementation of Gates using MOS Transistors

1. Realization of universal
gates
by
NMOS , PMOS , CMOS
By

2. nMOS ( n-channel MOSFET )
nMOS logic uses n-type metal-oxide-semiconductor field effect
transistors (MOSFETs) to implement logic gates and other digital circuits.
The composition of an NMOS transistor creates high resistance when a
low voltage is applied to it and low resistance when a high voltage is applied to it.

3. NOT gate by NMOS logic
❖ In the Q1 NMOS gate is connected with supply so it
is always in conducting mode.
Behave like a resistor
❖ When A is high Q2 will conducting ,Q1 conducts
due to i/p Vdd (high) and Vdd
Current directly goes to the ground , so Y becomes low.
❖ When A is low Q2 stop conducting , Q1 conducts
due to high i/p. so Vdd transfer to Y and output
becomes high.

4. NAND gate by NMOS logic
➢Q1 always conducts.
➢When both i/p are high Q2,Q3 start
conducting so Y=low.
➢When both are low Q2,Q3 stop
conducting and Vdd transfer to Y.
➢When one i/p is high so only one nMOS
conducts so only Vdd transfers to Y.
Q1
Q2
Q3
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Q1 Q2 Q3
on off off
on off on
on on off
on off off

5. NOR gate by NMOS logic
➢ If either input A or input B is high ,the respective MOS
transistor acts as a very low resistance between the output
and the negative supply, forcing the output to be low .
➢ When both A and B are high, both transistors are
conductive, creating an even lower resistance path to
ground.
➢ When both inputs are low, Q2 and Q3 transistors are off,
and output is high.
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

6. Disadvantage of NMOS logic
✓The worst problem is that a DC current flows through an
nMOS logic gate when the PDN is active, that is whenever the
output is low. This leads to static power dissipation even when
the circuit sits idle.
✓nMOS circuits are slow to transition from low to high. When
transitioning from high to low, the transistors provide low
resistance, and the capacitative charge at the output drains
away very quickly. But the resistance between the output and
the positive supply rail is much greater, so the low to high
transition takes longer. Using a resistor of lower value will
speed up the process but also increases static power
dissipation.
✓ The asymmetric input logic levels make nMOS circuits
susceptible to noise.

7. PMOS ( p-channel MOSFET )
PMOS logic uses p-type metal-oxide-semiconductor field effect
transistors (MOSFETs) to implement logic gates and other digital circuits.
The composition of a PMOS transistor creates low resistance when a low voltage
is applied to it and high resistance when a high voltage is applied to it.

8. NOT gate by pMOS logic
➢When A is high pMOS stop conducting
and Y becomes low.
➢When A is low pMOS starts conducting
and Vdd transfers to Y and it becomes
high.

9. NAND gate by pMOS logic
➢ Vdd will not trasfer to Y only
when both A and B are high. In this
case Y becomes low.
➢ If any of the inputs are high Y
becomes high.

10. NOR gate by pMOS logic
➢When both inputs are low then both
will conduct and Y becomes high.
In other cases the Y becomes low.

11. Disadvantage of PMOS logic
➢ Resistance between the output and the negative supply rail is much
greater, so the high to low transition takes longer.
➢ Using a resistor of lower value will speed up the process but also
increases static power dissipation.
➢The asymmetric input logic levels make pMOS circuits susceptible
to noise.

12. CMOS ( complementary -MOS )
➢CMOS was also sometimes referred to as complementary-symmetry
metal–oxide–semiconductor .
➢both N-type and P-type transistors are used to realize logic functions.
➢Two important characteristics of CMOS devices are high noise
immunity and low static power consumption.
➢CMOS devices do not produce as much waste heat as other forms of
logic.

13. NOT gate by CMOS logic
When the input A is low,
the NMOS transistor has high resistance so it
stops voltage from leaking into ground,
while the PMOS transistor has low resistance so
it allows the voltage source to transfer voltage
through the PMOS transistor to the output.
The output would therefore register a high
voltage. Vice versa
Ground=

14. NAND gate by CMOS logic
➢If both of the A and B inputs are high,
then both the NMOS transistors will
conduct, neither of the PMOS transistors
will conduct, and a conductive path will be
established between the output and Vss
(ground), bringing the output low.
➢If either of the A or B inputs is low, one of
the NMOS transistors will not conduct, one
of the PMOS transistors will, and a
conductive path will be established
between the output and Vdd (voltage
source), bringing the output high.
<-pMOS
<-nMOS