1. Impact of GND-PTH Stitches in
DDR3/GDDR3/GDDR5 Memory Controller
Packages
Hany Ahmad and Amolak Badesha
Agilent Technologies Inc.
5301 Stevens Greek Boulevard, Santa Clara, California, 95050
Abstract— DDR3 and GDDR3/5 memory technology running in including dynamic-I/O-buffer impedance. In this paper, we
the Giga-bit range require 3D EM accurate modeling of RF combine the different technology-models (MoM S-parameters
phenomena such as the impact of GND-PTH stitches (Ground of MCH-PKG, MB & DIMM + BSIM4 models of the I/Os +
Plated Through Hole) used to connect reference ground-planes in VNA measured S-parameters of DIMM-connector) in the
the Memory controller packages (MCH-PKG). Cost-reduction time-domain convolution-engine of ADS (Agilent EEsof
requires minimizing the number of layers and vias on MCH-
Advanced Design System) to study the impact of GND-PTH
PKG (micro-vias and PTH). Layout-Designers usually revert to
reduce the GND-PTH without studying the impact on the on data eye-opening as well as on Radiated-Emission of a
performance. In this paper, Method of Moments (MoM) is used DDR3 two-SODIMMs/channel running at 1.33GB/s.
to study the impact of GND-PTH on data eye-opening as well as
on Radiated-Emission of a DDR3 two-SODIMMs/channel II. METHOD OF MOMENTS PROVIDING DESIGN-
running at 1.33GB/s. GUIDELINES FOR MEMORY-CONTROLLER LOW-COST
PACKAGES
Keywords-component; DDR3, GDDR3/5, Memory-controller- A. Memory System Definition and Establishing Correlation
package, Method of Moments, GND-PTH, Radiated-Emission, eye- Cutting corners, caused by speed-of-light products,
diagram, Radiated-Emission of memory-channel, Antenna-Gain,
during the design process may result in neglecting to model
Convolution time-domain ADS engine.
critical phenomena such as GND-PTH causing eye-collapse
and loss of memory performance due to Return-Path-
I. INTRODUCTION Discontinuity (RPD). In this paper we will show the
High-Speed-Digital Designers face every day a importance of GND-PTH on MCH-PKG for DDR3 two-
tremendous challenge of high-performance interconnect- SODIMMs/channel in a notebook memory system as shown in
channel design constrained by low-cost products while Figure 1. We used frequency-domain MoM [1] to study the
pushing for speed-of-light time to market. Top-notch memory sensitivity of RPD in terms of proximity and number of GND-
technology (Rambus, DDR3, GDDR3 and GDDR5) running at PTH. As a result, we can develop routing guidelines for the
above 1.067GB/s with mm-wave spectral-content (<100ps minimum GND-PTH requirements on MCH-PKGs for data
rise/fall-times) needs full-wave EM modeling of Return-path- signals of the memory channel enabling cost-reduction.
discontinuity (RPD) such as the impact of data-signals
changing layers and changing reference ground-planes in the
MCH-PKG. Layout-Designers tend to reduce the cost of
MCH-PKG by reducing the number of layers and also the
number of vias including GND-PTH. No single
process/method can model the complete memory channel
accurately: Frequency-domain full-wave EM modeling is
required to capture RF effects of the memory channel and is
used to optimize the channel performance in terms of ISI, x-
talk, jitter, monotonicity, eye-opening as well as Radiated-
Emission. Method of Moments (MoM) is best to model
accurately the interconnects on multi-layer structures in the Fig. 1 Notebook with two-SODIMMs/channel. Increased Density and pressure
MCH/SDRAM package, Motherboard (MB), and Memory- for cost-reduction leads to high-risk design especially for memory-channel.
modules (DIMM) while FEM or VNA measurements are best
for modeling DIMM connectors. Transistor models (BSIM4) First, a correlation of the MoM S-parameter model
are best to capture the I/O buffers’ critical parameters for a GDDR3 data-signal on 12-layer PCB is performed:

2. comparing to VNA measurements up to 20GHz on the data-
signals as shown in Fig. 2-a.
Fig 3 cookie cutter of the 8-layers controller package with MOM.
Fig. 2-a S-parameter Insertion-Loss Correlation of VNA measurements
with Momentum Simulations on a data-signal for the GPU-card up to 20GHz.
Establishing correlation for S-parameter modeling of
passive-interconnects sets up the required discretization
parameters of MoM to extract accurate models for PCBs and
packages in the frequency range of interest.
The interconnecting system of the memory channel in
Figure 2-b is consisted of: The controller package,
Motherboard (MB) and SODIMMs (each is 8-layers) are all
modeled using S-parameters with MoM. The connector S-
parameter is obtained from VNA measurements noting that it
can be also modeled accurately using FEM [2].
Fig. 4 data signals (blue 11-signals) routed from die-bumps on layer-1 to
Fig. 2-b Interconnecting system for two-SODIMMs/ch. MOM used for the layer-3 as symmetric-Stripline referencing ground planes layers-2 (red plane)
multi-layer PCBs while VNA measurements is used for the connector. and 4 (brown plane).
B. Memory-Controller Package Modeling
Then the data nets are routed on layer-6 changing
A 3D EM modeling of the package is performed using reference ground-plane from layers-2/4 to ground-plane layer-
MoM as shown in Figure 3. We selected a portion of the 5 with ground stitches GND-PTH as shown in Figure 5 where
package encompassing a byte-lane (11-signals: 8-data-signals the core of 800um is located between layers-4 and 5.
and Strobe-deff-signals: DQS/DQS# and Data-Mask: DM)
that is at least 5λ away from all signals and vias where λ is
computed at the main harmonic of the channel (0.8GB/s:
minimum frequency of DDR3 technology). Data nets are
routed from the die-bump on layer-1 to layer-3 as shown in
Figure 4 where the ports are extended from the signal nets to
the ground-bumps on layer-1. Data nets are majorly routed as
symmetric-stripline with 30um referencing both ground-planes
on layers 2 and 4 to achieve the required impedance target of
40-ohms.

3. _3PT _m _a..S(1,3))
H om
m5
freq=3.155GHz
dB(S(1,3))=-46.210
dB(MCP89E_S1_1437BGA35mm8L_073109_final_release_Feb_25_2011_800um_3PTH_mom_a..S(1,4))1_1437B A35m 8L_073109_final_release_Feb_25_2011_800um
m4 m3
_2011_4 _a..S(1,3))
ind Delta= -3.151E8 ind Delta= -1.916E8
0
dep Delta=10.111 dep Delta=27.733
Delta Mode ON Delta Mode ON
pm
m3
-20
m4
(S(1,3))
-40 m5
dB(M _PK _0_P _FTH eb_16
dB
-60
-80
CH G
-100
m
0 2 4 6 8 10 12 14 16 18 20
freq, GHz
G
Fig 5 data nets change routing from layer-3 to layer-6 (blue routing) and Fig. 7 near-end x-talk studying the impact of GND-PTH stitching showing ~
changing referencing from ground-planes layers-2/4 to ground-plane layer-5 30dB x-talk increase due to lack of GND-stitching at 3GHz.
dB(M 89E_S
(red plane). GND-PTH are shown as blue-squares on the brown ground-plane
layer-4.
CP
m8
freq=2.994GHz
dB(S(1,4))=-45.739
Accurate 3D EM modeling of the pads, micro-vias, GND-
m7
PTH, interconnects, reference ground planes with layer ind Delta= -1.543E8 m6
ind Delta= -5.144E6
dep Delta=9.876
transition along with ground stitching are all required in such
dB(MCH_PKG_0_PTH_Feb_16_2011_4pm_a..S(1,4))
Delta Mode ON dep Delta=22.955
Delta Mode ON
data rates where the rise/fall times are in the range of mm- 0
wave power-spectral-density < 100ps at the die-bump.
-20 m6
III. GND-PTH IMPACT ON INSERTION-LOSS, NEXT (NEAR- m7
m8
dB(S(1,4))
-40
END CROSS-TALK0 AND FEXT (FAR-END CROSS-TALK)
-60
We will study the impact of ground stitching required
on the controller package when data-nets change reference -80
planes across the core of the MCH-PKG to reach the MCH-
-100
balls from the die-bumps as these signals are routed as single- 0 2 4 6 8 10 12 14 16 18 20
ended even running at such Giga-bit data rates to drive low- freq, GHz
cost memory technology. How many ground stitching is Fig. 8 far-end x-talk destructive impact of lack of GND-PTH stitches showing
required around signal transitions? How far need they be ~ 20dB more x-talk at 3GHz.
away from signal transition? This is an important design
guideline for memory channel designers as it has a direct Running 3D EM modeling was critical to capture the
implication on the performance (eye-opening and radiated- destructive impact of lack of GND-PTH stitches pushed by
emission) and cost of the controller package. cost-reduction of the MCH-PKG that shows excessive x-talk
reaching 30dB for near-end and almost 20dB for far-end (at
Figure 6 shows the Insertion-Loss (IL) of the data- 3GHz). Why does the x-talk deteriorate a lot due to lack of
nets for the controller package when all GND-PTH stitches GND-PTH when signals change layer from layer-3 to layer-6
(15 GND-PTH) exist (red signals) compared to the case of all going to the MCH-balls? Plotting the surface current density
GND-PTH removed (pink) and compared to the case of only Js (Js = n x H) on the reference planes shows the reason
3-PTH exist (blue). We can see almost 0.5dB delta when all behind such explosion of the x-talk as we found the return-
GND-PTH removed for the IL at 2.5GHz which may seem current uses the closeby signal-PTHs (least-inductive-path) of
fine compared to the cost-saving of removal of 15 GND-PTH the neighbor data nets to move from ground-plane layer-4 to
for an 8-layers 800um package technology. However, a look at ground-plane layer-5. The surface electric-current Js on
the near-end (NEXT) and far-end x-talk (FEXT) as shown in GND-plane layer-4 changes into displacement current Jd in
Figures 7 and 8 clarifies the destructive impact of lack of the gap between GND-Plane of layer-4 to the pad of the
B C 8 E S _ 4 7 G 3 m 8 _ 7 1 9 fin l_ le s _ e _ 5 2 1 _ 0 u _ P H m m a (1 ))
d (M P 9 _ 1 1 3 B A 5 m L 0 3 0 _ a re a e F b 2 _ 0 1 8 0 m 3 T _ o _ ..S ,2
GND-PTH on the x-talk. Signal-PTH then to surface electric-current Js again on the
Signal-PTH of the signal down to Layer-5 and then move back
with similar mechanism to layer-5 reference GND-plane as
d (M H P G 0 P H F b 1 _ 0 1 4 m a (1 ))
B C _ K _ _ T _ e _ 6 2 1 _ p _ ..S ,2
0
-1
shown in Figures 9-a and 9-b below.
-2
B (1 ))
d (S ,2
-3
-4
-5
-6
-7
0 2 4 6 8 10 12 14 16 18 20
freq, GHz
Fig. 6 Insertion-Loss and near-end/far-end x-talk studying the effect of GND-
PTH stitches around signal transitions.

4. 10GHz as shown in Figure 11 below and B-eye-diagram
analysis as shown in Figures 12-a and 12-b .
Fig. 9-a shows the surface electric-current Js couples to displacement current
Jd to the PTH of the closeby signal-PTH causing excessive x-talk caused by
the lack of GND-PTH.
Fig. 11: Voltage-transfer function for two-SODIMMs/channel with R/C-F
populating both slots.
Figures 12-a & 12-b shows the comparison of eye-
opening impact of GND-PTH running at 1.33GB/s. We can
see clearly the impact of excessive x-talk on eye-opening in
terms of both voltage-margin and timing-margin.
1.2
1.0
Eye_Probe9.Density
Eye_Probe8.Density
Eye_Probe7.Density
Eye_Probe6.Density
Eye_Probe5.Density
Eye_Probe4.Density
Eye_Probe3.Density
Eye_Probe2.Density
Eye_Probe1.Density
Fig. 9-b The surface current on the excited signal-PTH as well as on neighbor
signal-PTH as well as on GND-PTH vias.
0.8
IV. EYE-OPENING IMPACT OF EXCESSIVE CROSS-TALK BY
LACK OF GND-PTH ON MEMORY-CONTROLLER-PACKAGES 0.6
MoM is also used for 3D EM modeling of the MB
routing as well as the SODIMMs R/C-F which is a heavy 0.4
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
loading memory configuration as shown in Figure 10 below. time, nsec
1.0
EyeDiff_Probe1.Density
0.5
0.0
-0.5
-1.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
time, nsec
Fig. 10 MOM S-parameter modeling of MB and SODIMMs R/C-F Fig. 12-a showing the eye-opening for the original MCH-PKG with 15 GND-
PTH at 1.33GB/s.
The different technology models (S-parameters MoM
of MCH-PKG, MB and SODIMMs as well as VNA
measurement of the SODIMM connector) along with BSIM4
modeling of the I/Os are combined in a ADS-schematic editor
enabling to perform: A- voltage transfer function analysis
(AC-sweep) to study the complete channel performance up to

5. 1.2
1.2 1.1
1.0
Eye_Probe9.Density
Eye_Probe8.Density
Eye_Probe7.Density
Eye_Probe6.Density
Eye_Probe5.Density
Eye_Probe4.Density
Eye_Probe3.Density
Eye_Probe2.Density
Eye_Probe1.Density
1.1
1.0
Eye_Probe9.Density
Eye_Probe8.Density
Eye_Probe7.Density
Eye_Probe6.Density
Eye_Probe5.Density
Eye_Probe4.Density
Eye_Probe3.Density
Eye_Probe2.Density
Eye_Probe1.Density
0.9
0.9 0.8
0.8 0.7
0.7 0.6
0.6 0.5
0.5 0.4
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.4
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 time, nsec
time, nsec
1.0
1.0
EyeDiff_Probe1.Density
0.5
EyeDiff_Probe1.Density
0.5
0.0
0.0
-0.5
-0.5
-1.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
-1.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 time, nsec
time, nsec
Fig. 13-b DDR3-1.067GB/s data eye for the case of lack of GND-PTH
Fig. 12-b showing the eye-opening for the modified MCH-PKG without showing marginality even down-binning at 1.067GB/s.
GND-PTH at 1.33GB/s.
Using the JEDEC standard [3] eye-mask for DDR3 GND-PTH on MCH-PKG are shown to be very
memory channel (trapezoid from ViH/L(AC)=Vref+/=175mV critical for enabling DDR3 memory system operation at high-
to ViH/L(DC)=Vref+/=100mV) shows that the original data rates such as 1.33GB/s. What is the minimum number of
package (15 GND-PTH) passes eye-mask requirements at GND-PTH to enable 1.33GB/s operation while performing
1.33GB/s with a minimum of 95ps for DQ-2-DQS setup cost-reduction on the original-package? Figures 14-a and 14-b
margin (Figure 13-a) while the lack of GND-PTH causes show successful operation at 1.33GB/s with three GND-PTH
failure of eye-mask which can lead to memory speed down- reduction down from fifteen GND-PTH with worst-case hold-
binning to 1.067GB/s (as shown in Figures 13-b with worst- margin of 55ps with a loss of 40ps compared to the worst-
case hold-margin of -30ps), therefore, a big loss of setup margin of 95ps with fifteen GND-PTH vias. Figure 16
competitive advantage. shows that the GND-PTH is able to carry the return-path
current therefore reducing the amount of x-talk caused by such
return-path current travel through the signal-PTH.
m1
Index=2.000
DQ_DQSSkewSetupFal l .DIM M 1_62=96.929
260
D _ Q Se H ld is . I M_ 3
QD S k w o R eDM 1 6
240
220
200
180
160
140
120
m1
100
80
1. 0 1.5 2.0 2. 5 3. 0 3. 5 4.0
Index
Fig. 13-a DDR3-1.333GB/s eye-mask Setup/Hold margins shows worst setup
margin of ~ 95s with 15 GND-PTH.

6. 1.2
1.1
1.0
Eye_Probe9.Density
Eye_Probe8.Density
Eye_Probe7.Density
Eye_Probe6.Density
Eye_Probe5.Density
Eye_Probe4.Density
Eye_Probe3.Density
Eye_Probe2.Density
Eye_Probe1.Density
0.9
0.8
0.7
0.6
0.5
0.4
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
time, nsec
Fig. 15 showing the location of the most critical GND-PTH per byte lane
reducing 12 GND-PTH vias.
1.0
EyeDiff_Probe1.Density
0.5
0.0
-0.5
Fig. 16 Surface current on Signal-PTH and return-current on the neighbor
GND-PTH that is enough to provide successful operation with 3 GND-PTH
-1.0 instead of 15 GND-PTH per byte lane.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
time, nsec
Further analysis using MoM will show the comparison of
the Antenna-Gain of the MCH-PKG with 15 GND-PTH vs.
Fig. 14-a DDR3-1.33GB/s eye diagram for three GND-PTH cost-reduction lack of GND-PTH vs. 3 GND-PTH to study the impact on
down from 15 GND-PTH vias. Radiated-Emission.
V. CONCLUSION
m1
300
Index=
4.000
DQ_DQSSkewHol dRi se.DIM M 1_61=55.984 The paper shows the importance of driving design-
guidelines for GND-PTH on MCH-PKG as it has a destructive
D _ Q Se H ld is . I M_3
M 16
250
impact on x-talk due to the return-current uses the neighbor
QD S k w o R eD
200
Signal-PTH as least-inductive return-path hence causing
150
excessive x-talk that collapse the data eye at high-data rates.
100
m1
50
1. 0 1. 5 2. 0 2. 5 3. 0 3. 5 4. 0
VI. ACKNOWLEDGEMENT
Index
Special thanks to Giga-Test labs for S-parameter VNA
measurements.
Fig. 14-b DDR3-1.33GB/s eye-mask Setup/Hold margin with worst-case
hold-margin of 55ps. VII. REFRENCES
[1] Harrington RF, Field Computation by Moment Methods, The MacMillan
Figure 15 shows the location of the three GND-PTH Co., New York, 1968 .
that led to successful operation at 1.33GB/s and also enabled [2] Yue Yan Pramanick, P., “Finite-element analysis of generalized V- and
W-shaped edge and broadside-edge-coupled shielded microstrip lines on
cost-reduction of twelve GND-PTH per byte-lane, therefore, a anisotropic medium,” IEEE-MTT transactions, vol. 49, issue # 9, 2001, pp.
total reduction of ninety-six GND-PTH for the DDR3 memory 1649-1657.
channel routing on MCH-PKG (eight-byte-lanes). The cost [3] DDR3 SDRAM JEDEC Standard, JESD79-3E
reduction can be seen further with multiple channels on the
MCH-PKG.