There is a growing demand for memory bandwidth, FPGAs can help.

1. Revolutionizing System Memory Bandwidth

2. PROGRAMMABLE SOLUTIONS GROUP | Intel® ConfidentialProgrammable Solutions Group
WhatiSanfpga?
2
• An advanced, multi-function accelerator
• Flexible for highly differentiated products
• Reprogrammable as market dynamics or standards change

3. 3
Need for Memory Bandwidth Is Critical
HPC
8K Video
Networking
RADAR
Financial
MemoryBandwidth
Evolution of Applications Over Time
Growing
Memory
Bandwidth
Gap

4. 4
Need for Memory Bandwidth Is Critical
HPC
8K Video
Networking
RADAR
Financial
Example Applications Required Bandwidth
(GBytes/second)
Data Center 200
HPC, Custom Server 512 to 1000
HPC, Radar 400 to 1000
8K Video 172 to 432
Communications Tester 300 to 500
Body Scanner 300 to 500

5. “Far” Memory with Discrete DRAM
5
System-In PackageDiscrete
 Lower bandwidth
 Higher power
 Largest footprint
✓ Highest bandwidth
✓ Lowest power
✓ Smallest footprint
Meets the memory bandwidth needs
of next-generation applications
Cannot meet requirements of
next-generation applications
“Near” Memory with DRAM SiP
E M I B
E M I B
DRAM
DRAM
FPGA
Package
Meeting the Memory Bandwidth Challenge

6. Intel Stratix® 10 MX DRAM System-in-Package (SiP)
6
Integrates DRAM with Intel® Stratix® 10 FPGA
▪ Unified Intel® Quartus® software and OpenCLTM design environment
10x more bandwidth versus current discrete solutions
▪ Up to 512 GB/s of peak memory bandwidth
Widely applicable in HPC, military,
broadcast, and communications
First Intel® FPGA SiP products enabled by EMIB technology
Only FPGA shipping with 16GB HBM and 58G XCVRs
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos

7. Further Information
7
White Papers
Intel® Stratix® 10 MX Devices Solve the Memory Bandwidth Challenge
Enabling Next-Gen Platforms with 3D SiP
Achieving the Highest Levels of Integration
Industry’s First Heterogeneous SiP Devices with HBM2 DRAM
Getting Started Documentation
Intel Stratix 10 MX (DRAM System-in-Package) Device Overview
Available at www.intel.com/stratix10

9. 9
LegalNotices&disclaimers
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Cost reduction scenarios described are intended as examples of how a given Intel-based product, in the specified circumstances and configurations, may
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© 2016 Intel Corporation.

10. 10
Configurationdetails
Stratix 10 512 GB/s HBM2 DRAM bandwidth
Calculation based on Stratix 10 MX HBM2 interfaces multiplied by the maximum HBM2 DRAM bandwidth per interface. Stratix 10 MX supports a maximum of 2
HBM2 DRAM stacks, with each interface supporting 256 GB/s of DRAM bandwidth for a maximum peak memory bandwidth of 512 GB/s. Actual memory
bandwidth will vary based on memory controller efficiency determined by specific workload characteristics and memory usage patterns.