Describing inputs of physical design along with examples in brief way

1. Inputs of VLSI Physical Design
(With Synopsys tools used a Example)
A.Sai Kishore.
Project Engineer
Cerium Systems
Assited by
Anantha Bhat

2. Physical Design
● It is the process of transforming a Logical description
(in form of Netlist) into the physical layout(finally in
form of GDS2) , which describes the position of cells
and routes the interconnection between them.

3. Some of the Inputs of Physical Design
● Defination; Scenario => Combination of Modes & Corners
● Gate level Netlist (Predominently .v format & Hierarchical)
● Logical Library to link the netlist: Standard Cells (ASCII .lib converted to Binary .db)
● Library to link the Macros in the netlist: (For Eg. Timing model)
● Physical libraries(.lef) ( MATCHING Physical cells & Logical views)
● For each of the desigm Scenario's
– Timing,logical and power libraries(ASCII .lib converted to Binary .db
– Technology file(.tf)
– TLUPlus(Binary .tlup from nxtgrd files)
– Constraints(.sdc) (Either as separate file or common file with scenario varibales)
OPTIONAL: UPF file if low power methodology is adopted
●
● Design Decisions & Methodologies
● Floor Planning constraints ( Like Utilization Ratio)
● List of Design Scenarios for optimization & clock tree phases
● List of Scenarios for timing signoff
● Prefered to have: Any reference Methodology Script/Design Flow to follow
● Methodology constraints & Design Objectives/priorities ( like use of Low vt,High Vt etc)
Plus For Top level Physical Design
● Pads location
●

4. Gate Level Netlist
● Once you synthesize RTL , we will see only gates
where connections make the intended logic what you
coded in RTL
● Since whatever we write in rtl eventually it must be
converted to basic gates no matter how complex
algorithm we write
● DC , RC are two commonly used tools to convert
RTL design into gate level netlist basically a .v or
.vhdl file

5. Gate Level Netlist

6. Timing,Logical and Power Libraries
● It is generally a .lib/.db file that contains timing
information of all the standard cells.
● Functionality information of standard cells
● Design rules like max transition,max
capacitance,max fanout
● In timing information,cell delays, setup and hold
time are present

7. Timing,Logical and Power Libraries
● Also contain leakage power for default cell,default
input voltage and output voltage
● It also contains a LM(logical model) view

8. Physical Libraries
● It is a .lef(library exchange format) file that contains physical
info of standard cells,macros.
● Pin information of standard cells
● Min. width and height of the placement rows
● Preferred routing directions
● Pitch of routing tracks
● It contains two views
CEL view: Useful at the time of tapeout
FRAM view: Useful at the time of place & route.

10. Technology File
● It is a .tf file which contains the name of the technology to be
used.
● It also contains physical,electrical characteristics of the layer
● Physical characteristics include min width,area of the layer
● Electrical characteristics include current density of the layer
● It also contains physical design rules like wire to wire spacing ,
min width between layers.

12. TLU+ File
● These files are generated or extracted from
.itf(Interconnect Technology Format)
● .itf file contains the interconnect details.It also
describes the thickness and physical attributes of
conductor and dielectric layers.
● The TLU+ files main function is to find out the R,C
parasitics of metal per unit length for calculating net
delays.

13. Constraints
● It is basically a .sdc file in Tcl-based format.
● SDC file contains basic commands,object access
commands,timing constraints,environment
commands,multi voltage commands
● SDC file also contains exceptions like multicycle
path,false path

19. Conclusion
● Aim of PD phase is to implement the logic
● Aim is to meet Area, Timing & Power goals
● Design planning, Power planning, Placement, Clock tree
synthesis & Routing and iterative optimization are stages
● Physical, Logical , Timing, Parasitic & power information
are inputs needed for algorithms
● Along with Design, above needs to be provided
● Design approches may vary. Methodlogy decisions will help
in implementation Engineers work