An introduction to the changes made in VHDL 2017. Presented at FPGA kongress.

1. redefine.digital.design: Helping you deal with complexity in VHDL and Verilog.
VHDL 2017.
Lieven Lemiengre
FPGA Kongress
2017-07-13

2. ● Chief R&D @ Sigasi
● Software guy
● Front-end compiler
○ VHDL
○ SystemVerilog
● VHDL Working Group
About me

3. ● Open IEEE group
○ bi-weekly meetings
● Prominent members
○ Jim Lewis (chair)
○ Rob Gaddi & Patrick Lehmann (vice-chair)
● http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome
○ Meeting minutes
○ All proposals
○ Join the WG reflector
VHDL Working Group

4. ● VHDL: long legacy, strong future
● Unique advantages
○ Find bugs early
■ Strong typing
■ Easy to analyse
○ Library focussed
■ “Growable” language
○ Portable designs
■ Deterministic simulation
■ Unambiguous, simple semantics
VHDL: Why?

5. VHDL 2017: Approach
Need to evolve
○ Users: more concise, easy to use, safer
○ Library developers: better abstractions, less restrictions
2014: VHDL 20xx proposals survey
1. Interfaces: Records with directions
2. Language ergonomics
3. Library features
4. Bugfixes

6. Evaluating proposals
a. Backwards compatibility
b. Feature complexity vs benefit
c. Interaction with other features
d. Implementation considerations
■ Performance
■ Compiler complexity
VHDL 2017: Approach

7. In this presentation
● Interfaces: Records with direction
● 5 Small features
● Library features
VHDL 2017

8. ● Interfaces are everywhere
○ AXI, SPI, I2C, …
● Current approaches
○ Repeat interface definition everywhere
■ Hard to maintain
■ Very verbose
○ inout record
■ Unsafe
○ Gaisler coding style:, record for each direction
■ Split record for every direction
■ Maintain different records with naming conventions
VHDL 2017: Records with direction

9. Definition
package p is
type if_record is record
data_in : std_logic_vector;
valid : std_logic;
data_out : std_logic_vector;
end record if_record;
end package p;
VHDL 2017: Records with direction

10. Definition
package p is
type if_record is record
data_in : std_logic_vector;
valid : std_logic;
data_out : std_logic_vector;
end record if_record;
view if_view of if_record is
data_in : in;
valid, data_out : out;
end view if_view;
end package p;
VHDL 2017: Records with direction

11. Long form
use work.p.all;
entity e is
port(
clk : in std_logic;
rst : in std_logic;
if : view if_view of if_record
);
end entity e;
VHDL 2017: Records with direction

12. Short form
use work.p.all;
entity e is
port(
clk : in std_logic;
rst : in std_logic;
if : view if_view
);
end entity e;
VHDL 2017: Records with direction

13. Converse
use work.p.all;
entity e is
port(
clk : in std_logic;
rst : in std_logic;
if : view if_view’converse
);
end entity e;
VHDL 2017: Records with direction

14. Converse
use work.p.all;
entity e is
port(
clk : in std_logic;
rst : in std_logic;
if : view if_view’converse
);
end entity e;
VHDL 2017: Records with direction
out -> in
in -> out
inout -> inout
buffer -> in

15. Constrained subtype
entity e is
generic(g : natural);
port(
clk : in std_logic;
rst : in std_logic;
if : view if_view of if_record (
data_in(0 to g), data_out(0 to g)
)
);
end entity e;
VHDL 2017: Records with direction

16. Arrays
type if_record_vector is
array (natural range <>) of if_record;
entity e is
port(
clk : in std_logic;
rst : in std_logic;
if : view (if_view) of if_record_vector(1 to 10)
);
end entity e;
VHDL 2017: Records with direction

17. package p2 is
type nested_if_record is record
nested_field : if_record;
valid : std_logic;
end record nested_record;
view nested_if_view of nested_if_record is
nested_field : view if_view;
valid : out;
end view nested_if_view;
end package p2;
VHDL 2017: Records with direction
Composition
package p is
type if_record is record
data_in : std_logic_vector;
valid : std_logic;
data_out : std_logic_vector;
end record if_record;
view if_view of if_record is
data_in : in;
valid, data_out : out;
end view if_view;
end package p;

18. Subprograms
procedure p(signal b : view if_view; i : integer);
function f(signal b : view if_view; i : integer)
return integer;
VHDL 2017: Records with direction

19. VHDL 2017: Records with direction
Instantiation
architecture a of top is
signal clk, rst : std_logic;
signal if_inst : if_record;
begin
lbl : entity work.e port map(
clk => clk;
rst => rst;
if => if_inst;
);
end architecture

20. ● VHDL 2017: Interface
○ Record + Mode view (+ Subtype)
● Highlights
○ Simple
○ Composable
○ Arrays of interfaces
○ Converse of a interface
○ As parameter on subprogram
VHDL 2017: Records with direction

21. 1. Sequential Blocks
p : process is
variable outer : integer := 0;
begin
b : block
variable inner : integer := 0;
begin
inner := inner + 1;
report inner’image; -- always 1
outer := outer + 1;
report outer’image; -- 1 2 3 4 5 ...
end block b;
end process p;
VHDL 2017: Small improvements

22. 1. Sequential Blocks
p : process is
begin
if condition then
variable v : integer := 10;
constant c : integer := 4;
begin
v := c * 3;
end if;
end process p;
VHDL 2017: Small improvements

23. 1. Sequential Blocks
p : process is
begin
for i in vect’range then
constant element : integer := vect(i);
begin
some_operation(element);
end for;
end process p;
VHDL 2017: Small improvements

24. 2. Ternary expressions
● constant DELAY : time := 3 ns when FAST else 5 ns;
attribute RAM_STYLE of RegFile : signal is
"distributed" when SMALL else "block";
● y <= a xor b after (3 ns when FAST else 5 ns);
● return when condition;
return a when condition else b;
VHDL 2017: Small improvements

25. 3. Function knows return size
● Before VHDL 2008
some_vector <= resize(another_vector, some_vector’length);
● VHDL 2017
✔ some_vector <= resize(another_vector);
✘ some_vector <= v & resize(another_vector);
VHDL 2017: Small improvements

26. 3. Function knows return size
● function to_unsigned(i : integer) return r : unsigned is
begin
return to_unsigned(i, r’length);
end function;
● unsigned_s <= to_unsigned(integer_value);
VHDL 2017: Small improvements

27. 4. Improved attributes
● Directly use attributes on an object
○ report o’subtype’image(o); -- VHDL 2008
report o’image -- VHDL 2017
○ type state_t is (a, b, c);
variable pos : natural;
pos := state_t’pos(a); -- VHDL 2008
pos := a’pos; -- VHDL 2017
VHDL 2017: Small improvements

28. 5. New APIs
● Improved file api
○ Open a file in READ_WRITE_MODE
○ Determine if a file is still open
■ file_state(f)
○ Determine & modify file size
■ file_size(f) and file_truncate(f, size)
○ Quickly move around
■ file_position(f), file_seek(f, offset), file_rewind(f)
VHDL 2017: Small improvements

29. 5. New APIs
● New directory api
○ Explore directory tree
○ Create files in directories
○ Create and delete directories
VHDL 2017: Small improvements

30. 5. New APIs
● New date/time api
○ std.env package
○ Local or UTC time
○ to_string(localtime);
= "2017-07-13T09:20:13"
VHDL 2017: Small improvements
type time_record is record
microsecond : integer range 0 to 999_999
second : integer range 0 to 61;
minute : integer range 0 to 59;
hour : integer range 0 to 23;
day : integer range 1 to 31;
month : integer range 0 to 11;
year : integer range 1 to 4095;
weekday : dayofweek;
dayofyear : integer range 0 to 365;
end record time_record;

31. 1. Proposals
● Improved generics
● Anonymous types
● Garbage collection
● Removed restrictions for protected types
● Generics on protected types
● Reflection API
VHDL 2017: Library features

32. 2. Use case: Generic data structures
type int_list is new generic_list
generic map(vect => integer_vector);
variable lst : int_list;
lst.addAll((1, 2, 3)); -- lst = (1, 2, 3)
lst.add(10); -- lst = (1, 2, 3, 10)
lst.index_of(3); -- = 2
lst.remove_all(2); -- lst = (1, 3, 10)
VHDL 2017: Library features

33. 2. Use case: Generic data structures
type int_to_string is new generic_map
generic map(key => integer, value => string);
variable lookup_table : int_to_string;
lookup_table.put(1, “this”);
lookup_table.put(8, “that”);
lookup_table.get(8); -- = “that”
lookup_table.exists(3); -- = false
VHDL 2017: Library features

34. 2. Use case: Generic data structures
● List
● Associative arrays
● Set
● Stack or Heap
● Graph
● ...
VHDL 2017: Library features

35. 3. Use case: Data conversions using reflection
● to_string(value’reflect)
● to_json(value’reflect)
● to_std_logic_vector(value’reflect)
VHDL 2017: Library features

36. 3. Use case: Data conversions using reflection + anonymous types
● to_string(value)
● to_json(value)
● to_std_logic_vector(value)
VHDL 2017: Library features

37. ● Enhanced records to describe complicated interfaces
● Streamlined everyday use
● Enable new libraries
Conclusion: VHDL 2017

38. Questions ?