Introduction to FPGA world

1. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA for
Dummies
Modern FPGA architecture

2. ESS | FPGA for Dummies | 2015-12-08 | Maurizio Donna
FPGA for Dummies
• FPGA Architecture:
 basic blocks (Logic, FFs, wires and IOs);
 additional modern elements;
• FPGA Programming:
HDL languages;
Design flow;
• FPGA DSP:
Arithmetic, FFT and filters;

3. ESS | FPGA for Dummies | 2015-12-08 | Maurizio Donna
FPGA for Dummies
• FPGA Architecture:
 basic blocks (Logic, FFs, wires and IOs);
 additional modern elements;
• FPGA Programming:
HDL languages;
Design flow;
• FPGA DSP:
Arithmetic, FFT and filters;

4. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
Field Programmable Gate Arrays
(FPGAs)
FPGAs initially were Similar to CPLDs, so a function to be
implemented in FPGA is partitioned into modules (each
implemented in a logic block) and then the logic blocks are
connected with the programmable interconnection: ARRAY of
logic GATES is the G and A in FPGA.
By way of a configuration file or bit stream, an FPGA can be
configured to implement the user’s desired function: this allows
customization at the user’s electronics bench, or even in the
final end product.
This is why FPGAs are FIELD PROGRAMMABLE.

5. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Architecture
The basic structure of an FPGA is
composed of the following elements:
 Look-up table (LUT): This element
performs logic operations
 Flip-Flop (FF): This register
element stores the result of the
LUT
 Wires: These elements connect
elements to one another, both
Logic and clock
 Input/Output (I/O) pads: These
physically available ports get
signals in and out of the FPGA.

6. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Architecture

7. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Architecture
Contemporary FPGA architectures incorporate the
basic elements along with additional computational
and data storage blocks that increase the
computational density and efficiency of the device.
The combination of these elements provides the
FPGA with the flexibility to implement any software
algorithm running on a processor.

8. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.

9. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.

10. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: memory
Using LUTs as registers does not provide enough
space or versatility, so the FPGA fabric includes
embedded memory elements that can be used
as random-access memory (RAM), read-only
memory (ROM), or shift registers. These
elements are block RAMs (BRAMs), LUTs, and
shift registers.
Using LUTs (logic) as a memories, is called
DISTRIBUTE RAM (more Granularity)
Included dedicated RAM components in the FPGA fabric are called
BLOCKs RAM
For large data storage, are available instead hard/soft memory controllers that
commercial memory standard (DDR, cubiq-memory, etc…)
EXTERNAL MEMORY (more Capacity)
Logic
block
Logic
block
Block
RAM
Block
RAM

11. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: memory
Single-Port
Block RAM
True Dual-Port
Block RAM
Simple Dual-Port
Block RAM
Block RAM Cascading
Example: Cascade block RAMs to build
bigger memory

12. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: memory
FIFO means First-In First-Out.
A FIFO is a structure used in hardware or software application when you need to
buffer data, and/or move data between different clock domain.

13. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.

14. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components:
Off-chip memory controllers
FPGA devices provide memory interface support, including serial and
parallel interfaces.
 Serial memory: Hybrid Memory Cube (HMC) is the latest technology;
 Parallel Memory: latest devices offer parallel memory support up to
high rate for DDR4 and supports a wide range of other protocols like
o DDR3 / DDR3L, LPDDR3;
o DDR2;
o Mobile DRAMs;
o QDRII+ SRAM;

15. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.

16. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: clocking
All synchronous designs need at least one external clock reference,
many designs require several clock sources!!!
In FPGA there are several layers of metallization to interconnect the
Logic, and there are special one to distribute the clocks to all the Flip
Flops (FF).
Modern applications have complex clocking requirements:
 Extremely high-performance clock signals;
 Support for multiple frequency domains across a wide frequency
range;
 De-skewing of clocks relative to one another;
 Low jitter and precise duty cycle to maintain the widest possible
data valid window;
 Lowest possible system power

17. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: clocking
A Phase Lock Loop (PLL) is a control system that uses a Controlled
Voltage Oscillator (VCO) to generates an output signal whose phase is
related to the phase of an input signal;
A Delay-Locked Loop (DLL) is similar to a PLL but instead of the VCO
to vary the frequency, introduce fixed delay to change the phase;
Both components could replicate and/or generate new clocks
combination, according to the input clock frequency.
PLL are more “clear” than DLL, but DLL are easier to integrate in logic
than PLL.

18. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.

19. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: High Speed
Tranceivers
To communicate between FPGAs or
to other devices, it’s more convenient
to use high speed differential
connection instead of parallel one, to
reduce noise spikes.
Many standard protocol use this
approach for the physical layer:
Fibre Channel, InfiniBand, PCI
Express, RapidIO, SkyRail ,
Gigabit Ethernet, etc…

20. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: High Speed
Tranceivers
 TX: From the FPGA
fabric a parallel bus is
encoded to increase the
robustness against the
noise and to reduce the
DC component and then
serialized;
 RX: the received
differential signal is used
to reconstruct the clock,
and then decoded and
re-parallelized.

21. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.

22. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: multiplier
XILINX Spartan 3 (2004) include on
the side of each BRAM a multiplier
block (18x18)

23. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: multiplier
Altera Cyclone II (2005) has one to three columns of
embedded multipliers; each embedded multiplier
can be configured to support :
 One 18 x 18 multiplier
 Two 9 x 9 multipliers

24. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: XtremeDSP
Starting with Virtex 4 family (2005),
Xilinx introduced DSP48 block for
high-speed DSP on FPGAs
Essentially a multiply-accumulate
core with many other features
x
+
x
+
A[n:0]
B[n:0] Y[(2n - 1):0]
Multiplier
Adder
Accumulator
MAC

25. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: XtremeDSP
Adder Out = (Z ± (X + Y + CIN))

26. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: DSP unit
Also Altera include in the Stratix III family (2006) a similar DSP Unit.

27. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.

28. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: Embedded
Microprocessor Cores
Xilinx Virtex-II Pro (2002)
includes a PowerPC™ 405
Core in the chip (
1. Processor Block
2. RocketIO Multi-Gigabit
Transceivers
3. Configurable Logic
4. IO
5. Digital Clock Managers
6. Multipliers and Block
SelectRAM

29. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: Embedded
Microprocessor Cores
Xilinx Zynq (2013) is an Innovative
ARM® + FPGA architecture for
differentiation, analytics & control.
 Zynq-7000 SoC uses a Dual-core
ARM® Cortex™-A9 MPCore™ with
CoreSight™ up to 1GHz;
 Zynq UltraScale+ MPSoC uses a
Quad-core ARM® Cortex™-A53
MPCore up to 1.5GHz with a Real-
Time Processing Unit - Dual-
core ARM® Cortex™-R5 MPCore
up to 600MHz

30. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
FPGA Components: Embedded
Microprocessor Cores
Also Altera has ARM® +
FPGA architectures:
 Arria 10 SoCs, includes a
dual-core ARM® Cortex™-
A9 MPCore™ hard
processor system (HPS);
 Stratix 10 FPGA and SoC
system includes ad-core 64
bit ARM® Cortex®-A53 hard
processor system up to 1.5
GHz;

31. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna
Questions

32. ESS | FPGA for Dummies | 2016-08-30| Maurizio Donna