1. Implementation of LadyBug CPU
Name : LadyBug II
Website : http://ladybugsystems.ir
Version : Second Implementation with bigger instruction set, previous implementation is available
on our website.
Instruction Set
Word size : 16 bit
Type : RISC
Code Operation Description
0000 NOT A, B Does bitwise NOT on A and B,
we can choose one them using a
mux.
0001 NEG A, B Makes 2’s complement of A and
B, we can choose one of them
using a mux.
0010 AND A, B Does bitwise AND on A and B.
0011 OR A, B Does bitwise OR on A and B
0100 ADD A, B Adds B to A
0101 SUB A, B Subtracts B from A
0110 SHLA, B Shifts A or B to left, we can
choose one of them using a
mux*.
0111 SHR A, B Shifts A or B to right, we can
choose one of them using a
mux*.
1000 MUL A, B Multiplies A and B.
1001 DIV A, B Division, A/B.
Registers
Register Description
A 16 bit input register
B 16 bit input register
C 16 bit output register
Carry register 16 bit output register, keeps carry of DIV or
MUL operations.
2. Register Instruction
Code Operation Description
1010 MOV B, A Moves value of A to B
1011 MOV A, B Moves value of B to A
1100 MOV A, C Moves value of C to A
1101 MOV A, Carry Moves value of Carry to A
NOTES:
*. As Shift is a unary operation, like NOT and NEG, we decided to use a multiplexer to choose
inputs of shifters.
Step by Step Implementation
1. ALU:
