1. Prathik R
E-mail: prathik.rpk@gmail.com
Mobile: 9945456050
Objective: To gain a dynamic and challenging role in the area of ASIC Design Verification that will offer the
best opportunity for further development of my abilities, skills and knowledge.
Professional Summary:
 2 years of experience in ASIC Design and Verification
 Hands on experience and training in Coverage Driven Verification (Functional and Code)
using SV/UVM
 Hands on experience in Assertion Based Verification
 Knowledge on USB3x link layer
 Knowledge on AMBA protocols
 Good analytical and debugging skills. Flexible to learn new technologies.
 Basic knowledge of Shell, Bash and Perl scripting
Technical Skills:
 Hardware Descriptive Language : Verilog
 Hardware Verification Language : System Verilog
 Verification Methodology : UVM, Saola
 Tools used for Verification : Synopsys VCS, Cadence Incisive, Questasim
 Version Control Tools : Design Sync and git
Work Experience:
 Currently working as Project Engineer in Wipro Technologies
Educational Qualification:
 M.Tech in VLSI Design and Embedded Systems from RNSIT, Bengaluru
 BE in Electronics and Communication from JNNCE, Shivamogga
Certification:
 PG Diploma in ASIC Design Verification from RV-VLSI, Bengaluru

2. Project Experience:
1. Functional verification of USB3x subsystem
Description – This subsystem has multiple ports which can be configured to the legacy
mode (USB2) or USB3 (5 GHz) or USB3.1 (10 GHz). Proprietary bus fabric related BFM
configures the Host controller or the device controller RTL and according to the
configurations done, different set of transfers happen across the RTL and the USB
endpoints via generic selection logic and the PHY.
Role – Debugging and root cause of the regression failures related to link layer and host controller.
2. Design and Verification of SoC based Network subsystem for automotive
Description – Use of Ethernet subsystem in car for advanced driver assistance systems
Role – Validation of IPs (Quality checks), SoC integration, File management through
design sync version control system, sanity checks on the integrated SoC (Register access
testcase), regression runs, functional debugs, Lint and CDC runs with debug. ECOs and
LEC runs with debug on non-equivalence.
3. Bugscope usage on IPs and validation of coverage at SoC level
Description – IP bugs at SoC levels are costly. In order to exhaustively verify IPs, a new
tool BugScope from Synopsys is used. This tool helps to validate the coverage and
generates SVAs which can be hooked up at SoC level and check whether the assertions fire
or not.
Role – Setup of Bugscope environment for the existing IP database and check the coverage
report. Dumping SVAs and bind then at SoC level to validate the quality of test suite.
4. Verification of the Ethernet Transmitter and Receiver
Description – Functionality of the Ethernet Protocol is checked using the SV/UVM
testbench architecture. Several directed testcases with random test sequence has been
coded and used in regression testing to get maximum coverage. Code coverage and
functional coverage for the verified design were reported.
Role – Writing verification plan and coding the testbench architecture in SV/UVM with
thorough understanding of the design specification.
Personal Details:
 Name : Prathik R
 DOB : 10/10/1990
 Nationality : Indian
 Contact Number : +91 9945456050
 e-mail ID : prathik.rpk@gmail.com