PCB schematic review techniques prior to release for layout

1. PCB review techniques
Rafe Husain
Thinkom

2. Extract netlist using a protel format

3. Edit netlist to remove parts description
• Protel format contains both netlist and partslist
• Use text editor to remove partslist. Del from start till netlist starts

4. Manually review netlist
• Look for singletons
• Semi singletons (signals with resistor/passives only)
• Non connected GNDs and PWR which should be one
• Data bus incongruities. IE if 16 bit data bus then all 16 wires should
have same number of connections

5. Examples of faults
• 5V disconnect

6. Data bus example 1
• SPI flash has 4 bit data bus but 2 bits have pull up other two dont

7. Data Bus example 2
• Review schematic to check on AM572X_QSPI_D2, D3
• Turns out the additional pullups are ok

8. Data bus 3
See data bus with 2 passives no drivers

9. Data bus 4
• Upon review schematics shows the problem.
• The bus net doesn’t match the individual net
• Bus is called GPMC_AD individual nets are called AM75xx_GPMC_AD

10. Other anomalies 1
• Signal only connected to passives (maybe ok needs to be checked)

11. Other anomalies 2
There are 2 independent jtags so need to check.

12. Other anomalies 3
• Upon investigation the pull down is misnamed and is pulling the
wrong jtag
• Should be JTAG_FPGA_TCK

13. Summary
• Review of netlist in protel format gives view from underside of
schematic
• Gives visibility to bugs and mistakes which would otherwise slip thru
causing many problems in debugging and test.
• A netlist review should be required before release of PCB for layout
• Another review should be done after layout