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Renjini.K
Professional Summary
Eight years of strong experience in feasibility analysis, design, development of Telecom products
using Verilog/VHDL. FPGA/ ASIC Design, and SoC Design, digital design techniques, design using
microprocessors and microcontrollers. Expertize in the design and validation of FPGA Boards.
Excellent analytical and problem solving skills.
Skill/ Tools
Languages : VHDL / Verilog HDL,C, HANDLE C.
Simulators : NC Verilog, ModelSim.
Synthesizers : Design Compiler, Sinplify Pro, Leonardo Spectrum, Xilinx
ISE 14.1, Altera Quartus-II, Lattice ISP Lever.
Revision management : RCS, Clearcase (multisite VOB), Bugzilla.
Processor Expertise : MSP430, ARM7,Freescale P1011,8051,RISC1200
Processor Bus architecture : AXI, AHB, APB (High and Low speed processor Bus).
Modeling tool : MATLAB.
Debugging : Chipscope pro, Signal Tap.
Academics
MTech in VLSI Design and Embedded System from Visvesvaraya Technological
University, Bangalore, Karnataka India 2016.
#15, 7th A Cross Garden Villas
Nagarbhavi Bangalore- 560072
+91 – 9980512941
renjinikbhat@gmail.com

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Work History
Company Name: Cyient Limited
Tenure: July 2012 to September 2013
Designation: Senior Technical Lead
Project Details
1. MAXIM FIR Filter Design and Verification:
Client: MAXIM
Design of MAXIM low pass filter based on the specification and spectral requirement targeted
for tcbn65_stdcells_hvt_v100_t25_typ with wire load zero and PVT value best 1.1 -40.
Responsibilities
Define the Design and verification flow definition for the low pass filter.
MATLAB model generation for the LPF filter response analysis.
The filter realization is direct form Transposed Poly phase structure.
Preparation of conceptual verification document which covers testbench implementation,
testcase implementation, RTL simulation, coverage and bug reporting mechanism.
The output of the DUT is compared with the C-Model of the transposed FIR structure and the
coefficients are taken directly from MATLAB and are stored in an array model outputs which
act as reference to the checker module and the output of DUT is compared with it to generate
pass/fail for each test cases.
2. USB2.0 EHCI test specification:
Client: Nihon Kohden
Enhanced Host Controller interface specification describes the register level interface for a
host controller for the USB revision 2.0. The task was to identify the feasible test cases for the
regression test of EHCI host.
Responsibilities
Prepared the EHCI test document which defines the specification for generic data flow,
register and CPU interface, Protocol, USB Interface, Power management, exceptions and
corner cases.

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3. OCELOT SoC integration and verification:
Client : CoE
The SoC incorporates the OR1200 V 1.2 of Open RISC Architecture with the processor being
the master initiating the communication with peripherals via AXI Bus and peripherals
connected to APB Bus communicating to processor with AXI2WB, WB2AXI & AXI2APB
modules.
Responsibilities
Integration of System Control, WDT, SPI modules.
Module Verification of WDT and SPI modules.
SoC Integration and design of SPI, System control logic and AXI to APB bridge using verilog.
OCELOT validation in Xilinx ML605 Development Board (5vlx50tff1136).
Company Name: Techmahindra Limited
Tenure: December 2006 to June 2012
Designation: Design Lead
Project Details
4. Fabric Card Interface Control FPGA:
Client : Benu Networks
Implementation of Fabric Card interface Control (FIC) FPGA for Fabric Control card (FCC).
The FIC FPGA generates reset and configuration signals, provides interface for Freescale
P1011 processor and asynchronous interface for Broadcom SAND chipset and provides
redundancy control signals and programming interface to FCC.
Responsibilities
Feasibility study of the design.
Prepare detailed design document on the implementation of the modules from specification.
Developed RTL modules in verilog and system verilog HDL for FIC FPGA (eLBC,
Asynchronous FE600 Processor Interface, reset generation and acquisition, power good signal
generation, interrupt).
Timing Closure using Quartus II and verification in Cadence NCSIM.
The FIC FPGA was targeted to cyclone-4-EP4CE15.

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5. Re-Design ofASIC to FPGA for LITESPAN 2000 DLC system
Client: Alcatel Lucent
Data Link controller and Tone Generator: Migrate AMI ASIC from Samsung 0.35u
STD90 technology to FPGA to cater the DCT ASIC obsolescence issue and rectify SRAM
timing issues on DCT card.
Design and implementation of Datalink controller and Tone controller for Litespan 2K
System. DCT is a major interface between the memory mapped input Output of the Terminal
Control Processor (TCP) and the serial format of the Time Slot Interchanger ‘s (TSI) TDM
buses.
Re-design of SONET formatter unit: Migration of 18 AMI ASICs in Sonet Formatter Unit
card in Litespan 2K/2K12 system to a single Lattice FPGA.STS-N (N=3,12) support.
The function of the SFU is to transmit and receive up to STS-N (N=3) signals multiplex up to
n STS payloads and perform SONET section, line overhead byte generation including
framing, pointer processing and parity check.
Responsibilities
Design changes to cater ASIC to FPGA migration.
Verified RTL for functionality and Post layout net list for timing.
Created a detailed test-plan to verify the functionality and verified the RTL as per the
test plan.
Functional test in the System level for the Litespan 2K/2K12 system.
Closely worked with the Board Design team for their implementation specific support.
Maintain the multisite VOB and clearcase revision control management.
6. Implementation ofPCS for 2BASE-TL FPGA
Client: CoE
The objective was to design and develop physical layer implementation for Ethernet over
voice grade copper (10PASS-TS and 2BASE-TL) for xDSL application
Responsibilities
Design and Implement PCS for 2BASE-TL.The 2 major function of PCS is MAC-PHY rate
matching and PME aggregation
Physical resource utilization estimation

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Architecture document preparation
Coding for the EFM PCS receiver
Synthesis and Implementation of the design using Xilinx Implementation tool, ModelSim
Provided guidance in designing RTL and Verifying the designed Blocks using ModelSim.
The design was targeted for Xilinx Virtex II pro
Company Name: Digipro System Pvt Limited
Tenure: March 2001 to February 2003
Designation: Member Technical Staff
Project Details
Client: CELOXICA
Development of IP cores for Celoxica using Handle C Language. The list of IP developed
includes Cordic, Encryption/Decryption using safer plus algorithm , PIT, 32 bit
adder/subtractors, 16 bit multipliers.
Professional Achievements
 Awarded the Best Team for the extra ordinary performance delivering timely and
excellent quality product (SFU2, ADS1U POTS, DCT ASIC) – Alcatel Lucent.
 Presented the final year MTech thesis work in the 7th National conference on Recent
trends in Electronics and communication Engineering (NCERTEC-15).
 Process document preparation for ASIC and FPGA life cycle.
 Participated in Various Xilinx University Program and successfully conducted trainings for
corporate on various Xilinx modules like Fundamentals of FPGA, Designing for performance,
Advance FPGA design techniques through Sandeepani school of VLSI design.
 Taken trainings in Synthesis and Primetime for corporates like TI, WIPRO.
 Involved in the HW lab Setup for Tier 1 Telecom customers.
 Participated in the International conference on circuits, Controls and Communications (CCUBE-
2013).
 Volunteered for National Conference on recent advances in communication networks-NCRACN-
2014.
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