Semiconductor Chip Industry Challenges & Trends 2.5D/3D IC Packaging Technology Overview 2.5D/3D IC Packaging Manufacturing Challenges 2.5D/3D IC Market Enablers: Factory Automation 2.5D/3D IC Market Opportunity

1. Semiconductor Manufacturing
2.5D/3D IC Market
Challenges & Opportunities
Rohan Hubli
October 16th, 2012

2. Rohan Hubli
Presentation Outline
1. Industry Challenges & Trends
2. 2.5D/3D IC Packaging Technology Overview
3. 2.5D/3D IC Packaging Manufacturing Challenges
4. 2.5D/3D IC Market Enablers: Factory Automation
5. 2.5D/3D IC Market Opportunity

3. Semiconductor
Industry Challenges & Trends
3

4. Rohan Hubli
Off-Chip vs. On-Chip Interconnect Gap
Source: TSMC

5. Rohan Hubli
Skyrocketing Chip Development Costs
Source: GLOBALFOUNDRIES

6. Rohan Hubli
The Solution: 2.5D and 3D IC
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7. Rohan Hubli
2.5D/3D Chip Assembly Options
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WSS: Wafer Support System, FC: Flip Chip, BOM: Bill of Materials

8. 2.5D / 3D IC
Packaging Technology Overview
8

9. Rohan Hubli
3D IC’s: Enabling Technologies
Source: Yole Research, 2012

10. Rohan Hubli
2.5D / 3D IC: Processing Steps
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TSV fabrication steps
Wafer Thinning & Bonding Steps

11. Rohan Hubli
3D IC TSV Processing Options
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Via Middle is Mainstream Today

12. Rohan Hubli
TSV Processing Steps
12
Source: Applied Materials, 2012

13. Rohan Hubli
ITRS 2.5D/3D TSV Roadmap
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14. Rohan Hubli
2.5D/3D IC Packaging: Start to Finish
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15. Rohan Hubli
2.5 D/3D IC Value Chain & Players
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16. Rohan Hubli
3D IC Processing Steps: Cost Breakdown
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Source: Yole Development, 2012
TSV Via Filling and Bonding steps together account for 75% of 3D IC Processing
Cost.

17. Rohan Hubli
2.5D / 3D IC Packaging Options
17

18. 2.5D/3D IC Packaging
Manufacturing Challenges

19. Rohan Hubli
TSV DRIE Process Complexity
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Source: SEMATECH, 2012

20. Rohan Hubli
DRIE Process: Etch Rate vs. Aspect Ratio
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In DRIE Process, chamber pressure and total flow have to be optimized
because both of them affect uniformity, selectivity and sidewall passivation
during etching.
W
D
Aspect Ratio = W/D
DRIE: Deep Reactive Ion Etching
Source: SPTS, 2012

21. Rohan Hubli
TSV Via Fill: Electrochemical Deposition Process
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 Most expensive and longest process time
 Requirements of Via Fill
1. Void-free Cu filling
2. Low Cu overburden
3. Low CoO (high throughput)
TSV Interconnect with Typical Failures

22. Rohan Hubli
Eliminating TSV Voids during ECD Process
Eliminating TSV voids during the Cu electrochemical deposition (ECD)
process requires reducing impurities in the ECD chemical solutions.
Source: UMC , 2012

23. Rohan Hubli
TSV Via Reveal Process
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Si recess-etch to about 50µm final Si thickness is required to expose all TSV’s
with ±1 µm variation for solder bumping.
 Key : No damage to silicon, liner or tip
 Critical : No copper residue on surface
Before After

24. Rohan Hubli
Grinding and CMP Process
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25. Rohan Hubli
Wafer Thickness
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26. Rohan Hubli
3D IC Bonding Approaches
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27. Rohan Hubli
3D IC Bonding Challenges
Device topography:
Device topography varies significantly from one device design to an
other and may range from 1 or 2µm, to more than 80µm in cases
where solder bumps are used as interconnects.
Bonding Challenges:
1. For bonding, viscous bonding material needs to be spray coated
at slow spin speeds to achieve desired uniformity and coating
thicknesses.
2. Non uniform coating of the bonding material (Ex: edges) can
result in overgrinding which may expose and smear vias.
3. Bonding between wafers (dies) must be free of voids due to
trapped air or impurities.

28. Rohan Hubli
3D IC Packaging: Manufacturing Defects
TSV Voids:
 During the fabrication of TSVs, (micro-)voids, for example due to q
uasi-conformal plating, might lead to (weak) opens in TSVs
 Ineffective removal of the seed layer might lead to shorts
between TSVs
Thermal Dissipation / Thermo-mechanical stress
 Due to the different Coefficients of Thermal Expansion (CTEs) of th
e various materials in the stack, the stack might suffer from ther
mo-mechanical stress, causing further malfunction.

29. Rohan Hubli
3D IC Packaging: Manufacturing Defects
Thermal Dissipation / Thermo-mechanical stress
 In densely packed stacks of thinned dies, the heat density might
pile up quite high, and has little way of escaping. The heat gener
ated might easily impact the correct operation of the various dies
, especially since some dies are more heat-sensitive (memory)
 Due to the different Coefficients of Thermal Expansion (CTEs) of
the various materials in the stack, the stack might suffer from
thermo-mechanical stress, causing further malfunction.
Source: IBM, IMEC, SEMATECH, ITRS

30. Rohan Hubli
2.5D/3D IC Reliability Issues
30
Source: ITRS, 2012

31. 2.5D/3D IC
Manufacturing Automation

32. Rohan Hubli
2.5D/3D IC Manufacturing Automation
Process Control
Solutions
TSV
Etching / Drilling
TSV
Via Fill
CMP &
Grinding
Bonding
Run 2 Run Control
Statistical
Process Control
Fault Defect
Classification
Recipe Management
Solution
Predictive Preventive
Maintenance
IC Root-Cause
Analysis
Root Cause Analysis of 2.5D / 3D IC Failures

33. Rohan Hubli
3D IC Root Cause Failure Analysis
3D IC
Root-Cause
Analysis
Memory
(Pre-Bond Test)
SOC
(Pre-Bond Test)
Memory
(Post-Bond Test)
SOC
(Post-Bond Test)
Die Level
(Sort, ETest, PCM, Inline Data )
Die1
DieN
Interconnect Test

34. Rohan Hubli
3D/2.5D IC Test and Assembly Value Chain
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Root-Cause Analysis

35. 2.5D / 3D IC
Market Opportunity
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36. Rohan Hubli
IC Packaging Market: 2011-2015
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 Market for TSVs will grow from 39 billion units in 2011 to 54 billion in 2015
 TSV Revenues will increase from $154 billion in 2011 to $214 billion in 2015.
 TSVs are typically found in FBGAs, BGAs and WLPs.
Source: New Venture Research, 2012

37. Rohan Hubli
3D IC Packaging Demand
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38. Rohan Hubli
3D IC Equipment Forecast
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39. Rohan Hubli
Global TSV Chip Wafer Forecast
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40. Rohan Hubli
2.5D Interposer Market Size
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41. Rohan Hubli
2.5D Interposer Wafer Forecasts
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42. Rohan Hubli
2.5D/3D Wafer Forecast (By End Applications)
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43. Rohan Hubli
FOWLP Unit Forecast Shipment by Industry
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FOWLP: Fan-Out Wafer Level Packaging

44. Rohan Hubli
DRIE Processed Wafer Shipment Projections
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DRIE Application Areas are all in High Growth Markets:
• MEMS (13% CAGR),
• Advanced IC Packaging (18% CAGR),
• Power Devices
Source: Yole Research, 2012
DRIE Equipment Vendors
• AMAT
• Lam Research
• Maxis
• Oxford Instruments
• Panasonic
• Samco
• SPTS
• TEL
• Ulvac

45. Rohan Hubli
2.5D/3D TSV Key Players
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Middle-end activity or revenues including TSV etching, Via Filling, RDL, Bumping,
wafer test & wafer level assembly

46. Rohan Hubli
2.5 / 3D IC : Call for Action
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1. Concentrated Industry Wide Effort
2. 2.5D/3D IC Requires Manufacturing Automation
3. 2.5D/3D IC Failure Analysis – Who, How and When
4. Cost, Cost, Cost - $$$
5. Embrace Lead Adopters- New Applications & Startups

47. THANK YOU
Rohan Hubli