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Toward Automatic Generation of Models with Probes from the SDL System Specification

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This document summarizes the automatic generation of Promela models with probes from SDL system specifications. It describes inserting probes into generated models to detect invalid states, semantic rule violations, and potentially erroneous executions. A case study on formally verifying the V.76 telecommunications protocol specification is presented, where probes revealed implicit signaling, ignored commands, and violations of temporal properties. The approach supports modeling SDL concepts like processes, data types, communication, and verification with the Spin model checker.

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Toward Automatic Generation of Models with Probes from the SDL System Specification University of Maribor Faculty of Electrical Engineering and Computer Science Boštjan Vlaovič , Ph. D. [email_address] Workshop on Formal Verification of Telecommunication Systems , Part I Zagreb, 5. 11. 2004 UM FERI
[object Object],[object Object],[object Object]
Overview ,[object Object],[object Object],[object Object],[object Object],[object Object]
Introduction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Specification and Description Language ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],SDL: Specification and Description Language Formal specification of a system in the SDL is unambiguous, clear and exact.
SDL Specification
Model Checking Technique system specification requirements model of the system model with probes formal verification tool SDL Promela claims, temporal formulas Şpin violation of the requirements counter-example
SDL Extended Finite Automata ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],simulation implementation formal verification Additional expansions: ,[object Object],[object Object],[object Object],[object Object]
Process Definition ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Total number of 34 definitions were used to describe SDL system
Data Types ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Formal specification of the automatic model generation is described by 40 algorithms in pseudo-SDL.
Promela Model of the System proctype dataLink__AtoB(pt__chan input; pt__pid parent){ pt__pid offspring, sender; byte pv__ptr, pv__cur; xr input; V76paramTyp V76par; goto ready; ready: end_1: do :: table_channum_ptr[input] > pv__cur -> table_channum_prio[input]=false; pv__cur++; pv__ptr=0; atomic{ do :: pv__ptr <= cv__buff-1 -> if :: else -> set__clear(); fi; pv__ptr++ ; :: else -> goto ready_start; od; } ready_start: if :: table_channum_prio[input]==true -> pv__ptr=0; do :: (pv__ptr <= cv__buff-1) && (table_channum_nsp[input].data[pv__ptr].prio==true) -> if /* PRIORITY INPUT */ :: else -> skip; fi; :: (pv__ptr == cv__buff) -> break; :: else -> pv__ptr++ od; :: else -> pv__ptr=0; do :: (pv__ptr <= cv__buff-1) -> if :: skip__save() :: else -> . . . }
Scientific Contributions (1) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Communication ,[object Object],[object Object],[object Object],[object Object],priključek We support additional path limitations with the use of the Via statement.
Analysis of potential receivers ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],SIGNALROUTE sr1 FROM P1 TO ENV WITH sig1; FROM ENV TO P1 WITH sig1; SIGNALROUTE sr2 FROM P2 TO ENV WITH sig1; FROM ENV TO P2 WITH sig1; CONNECT k1,k2 AND sr1, sr2; PROCESS P1; PROCESS P2; ENDBLOCK; BLOCK B2; SUBSTRUCTURE ; CHANNEL k22 FROM B22 TO ENV WITH sig1; FROM ENV TO B22 WITH sig1; ENDCHANNEL; CHANNEL k21 FROM B21 TO ENV WITH sig1; FROM ENV TO B21 WITH sig1; ENDCHANNEL; CONNECT k1 AND k22; CONNECT k2 AND k21; BLOCK B21; SIGNALROUTE sr1 FROM P1 TO ENV WITH sig1; FROM ENV TO P1 WITH sig1; SIGNALROUTE sr2 FROM P2 TO ENV WITH sig1; FROM ENV TO P2 WITH sig1; CONNECT k21 AND sr1, sr2; PROCESS P1; PROCESS P2; ENDBLOCK; BLOCK B22; SIGNALROUTE sr1 FROM P1 TO ENV WITH sig1; FROM ENV TO P1 WITH sig1; CONNECT k22 AND sr1; PROCESS P1; ENDBLOCK;
Communication
Scientific Contributions (2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Introduction of Probes to the Model ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],LTL: Linear Temporal Logic
Case Study – FV of protocol V.76 ,[object Object],[object Object]
System V76test
Block DLC[ab]
Model of the environment
Automatic Generation of Models ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Formal Verifi cation of the Model ,[object Object],[object Object],[object Object]
Corrections of the Specification
Inclusion of Probes ,[object Object],[object Object],[object Object]
Temporal properties ,[object Object]
Temporal properties
Scientific Contributions (3) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
 
Counter Example

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Toward Automatic Generation of Models with Probes from the SDL System Specification

  • 1. Toward Automatic Generation of Models with Probes from the SDL System Specification University of Maribor Faculty of Electrical Engineering and Computer Science Boštjan Vlaovič , Ph. D. [email_address] Workshop on Formal Verification of Telecommunication Systems , Part I Zagreb, 5. 11. 2004 UM FERI
  • 2.
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  • 7. Model Checking Technique system specification requirements model of the system model with probes formal verification tool SDL Promela claims, temporal formulas Şpin violation of the requirements counter-example
  • 8.
  • 9.
  • 10.
  • 11.
  • 12. Promela Model of the System proctype dataLink__AtoB(pt__chan input; pt__pid parent){ pt__pid offspring, sender; byte pv__ptr, pv__cur; xr input; V76paramTyp V76par; goto ready; ready: end_1: do :: table_channum_ptr[input] > pv__cur -> table_channum_prio[input]=false; pv__cur++; pv__ptr=0; atomic{ do :: pv__ptr <= cv__buff-1 -> if :: else -> set__clear(); fi; pv__ptr++ ; :: else -> goto ready_start; od; } ready_start: if :: table_channum_prio[input]==true -> pv__ptr=0; do :: (pv__ptr <= cv__buff-1) && (table_channum_nsp[input].data[pv__ptr].prio==true) -> if /* PRIORITY INPUT */ :: else -> skip; fi; :: (pv__ptr == cv__buff) -> break; :: else -> pv__ptr++ od; :: else -> pv__ptr=0; do :: (pv__ptr <= cv__buff-1) -> if :: skip__save() :: else -> . . . }
  • 13.
  • 14.
  • 15.
  • 17.
  • 18.
  • 19.
  • 22. Model of the environment
  • 23.
  • 24.
  • 25. Corrections of the Specification
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  • 29.
  • 30.  

Notes de l'éditeur

  1. 1