Journal of VLSI Design Tools & Technology (JoVDTT) is focused towards the rapid publication of fundamental research papers on all areas of VLSI Design Tools & Technology. Focus and Scope Covers Analog/Digital Integrated Circuits & Systems VLSI Architectures, Algorithms, Methods & Tools for Modeling Simulation, Synthesis & Verification of Integrated Circuits and Systems Embedded Systems; High-Level Synthesis for VLSI Systems Test Generation Algorithms, Physical Design Systems Engineering Heterogeneous Systems

1. Journal of
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10. 1. Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy
Shashank Gautam, Pramod Sharma 1
n n n
2. Design of Booth Encoded Multi-Modulus {2 -1, 2 , 2 +1} RNS Multiplier
Saguna Goel, Sakshi Bajaj, Amanpreet Kaur 7
3. Design of FPGA Based ALU Using Reversible Logic Gates
Vishal A. Wankhede, Ramprasad M. Gawande 15
4. Linearity Analysis of Traditional Single and Double Balanced Down Conversion Mixers
Akash I. Mecwan, N.M. Devashrayee 22
5. Development of System for Speech Enhancement using Combinational Adaptive
LMS on Reconfigurable Platform
Pradip C. Bhaskar, Prachi S. Gosavi 28
6. Design of High-Speed and Low-Power Carry Skip Adder
Gutlapalli Venkatrao, Motkuri Krishna 35
7. A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique
Srinibasa Padhy, B.S. Patro, Monica Swain, J.K. Das 45
8. Survey of System-on-Chip Modular Test Approach
Harpreet Vohra, Amardeep Singh 56
9. Design of Low Power Resistor Less Flash ADC for UWB Receiver Applications
Ankush Chunn, Rakesh Kumar Sarin 71
10.VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter
Minakshi M. Wanjari, Pankaj Agrawal, Ravindra Kshirsagar 88
ContentsJournal of VLSI Design Tools & Technology

11. JoVDTT (2016) 1-6 © STM Journals 2016. All Rights Reserved Page 1
Journal of VLSI Design Tools & Technology
ISSN: 2249-474X (online), ISSN: 2321-6492(print)
Volume 6, Issue 3
www.stmjournals.com
Area Efficient Layout Design of Two Bit Magnitude
Comparator Using Novel Strategy
Shashank Gautam*, Pramod Sharma
Department of Electronics and Communication Engineering,
Raja Balwant Singh Engineering Technical Campus, Bichpuri, Agra, Uttar Pradesh, India
Abstract
The development of digital circuits, digital signal processors and other data processing
integrated circuits, comparators are challenged by large area consumption. Comparator is
most basic and fundamental component that performs comparison operation. This paper
proposes a new approach to design an area efficient two bit magnitude comparator.
Comparison is done on the grounds of area and power consumed between circuit designed by
novel strategy and preexisting CMOS technique. The novel technique described in this paper
is found to be effective and efficient to reduce the chip area.
Keywords: Two bit, magnitude comparator, layout design, chip area, power consumption
INTRODUCTION
Basically, comparator is a logic circuit that is
able to compare the amplitude of the input
lines and provides the corresponding result at
the output [1, 2]. The output obtained is
basically the relation between the two
numbers, i.e. greater than, less than equal to.
Fig. 1: Block Diagram of N bit Magnitude
Comparator.
Figure 1 shows the block diagram of an N-bit
magnitude comparator. It receives two N bit
numbers as input and gives output as (A>B),
(A=B) and (A<B).Magnitude Comparator
circuit is widely used in instrumentation and
measurement circuits and is also a significant
part of analog to digital convertor (ADC) [3].
Magnitude comparator can be of any N number
of bits where N is equal to 1, 2, 4, 8, 16, etc. [4]
In this paper, an efficient strategy is proposed
which is able to reduce the chip area of two bit
magnitude comparator to very large extent.
TWO BIT COMPARATOR
Two bit magnitude comparator is a
combinational logic circuit. This circuit has three
output lines, i.e. (A greater than B), (A equal to
B) and (A less than B) [5]. For this type of
arrangement truth table consists of four inputs
variables and sixteen entries as shown in Table
1. Table 1 provides the output state for every
possible values of input of two bit magnitude
comparator. On simplification of the above truth
table by K-map the output of the two bit
magnitude comparator is obtained which is used
to design the circuit of two bit magnitude
comparator by CMOS technology. Figure 2
shows the circuit diagram of two bit magnitude
comparator designed by CMOS technology.
Figure 3 shows the waveform diagram of two bit
magnitude comparator showing different states
of inputs and outputs.

12. JoVDTT (2016) 7-14 © STM Journals 2016. All Rights Reserved Page 7
Journal of VLSI Design Tools & Technology
ISSN: 2249-474X (online), ISSN: 2321-6492(print)
Volume 6, Issue 3
www.stmjournals.com
Design of Booth Encoded Multi-Modulus {2n
-1, 2n
, 2n
+1}
RNS Multiplier
Saguna Goel1,
*, Sakshi Bajaj2
, Amanpreet Kaur3
Department of Electronics and Communication Engineering, Thapar University,
Patiala, Punjab, India
Abstract
Multiplication, a very important arithmetic operation, is finding a great use these days in
various applications (especially DSP, multimedia and image processing). Due to advances in
technology and increasing needs for high-speed calculations, it has become really necessary
and important to design a fast efficient multiplier. A productive method to speed up the
multiplication is reduction in the Partial Product (PP) array. In this paper, the design of 8, 16
and 32 bit RNS multiplier based on Radix-4 Booth encoding is presented. The results of
simple Booth multiplier are compared to a Booth encoded Residue Number System (RNS)
multiplier. A significant improvement in terms of speed and area utilization is observed when
Booth is applied to RNS. Pipelining has been incorporated in the architectures to boost the
speed further. The designs are described in Verilog HDL, simulated and synthesized on Xilinx
14.5, targeted on Spartan 3E FPGA device.
Keywords: Booth algorithm, Radix-2, Radix-4, Radix-8, multiplication, Residue Number
System, pipelining
INTRODUCTION
The process of Multiplication (repetitive
addition), is gaining high importance in
various applications, particularly in the field of
Digital Signal Processing (DSP) for the
execution of complicated high-speed
computations [1]. There are three basic steps
involved in the process of Multiplication: 1)
Generation of Partial Products (PPG) 2)
Reduction in Partial Products (PPR) and 3)
Addition of Partial products. Multipliers are a
very important part in most processors and
generally have large area consumption and
high latency. They are slowest component of a
system. Therefore, upgrading area and speed is
a major issue while designing a multiplier. A
number of techniques have been proposed to
drive the speed of multiplication. Also, various
algorithms to reduce number of Partial
Products have been proposed.
Booth encoding is one such technique and is
most frequently used. Booth encoding
increases the multiplication speed and thus
makes the arithmetic fast. Radix-4 Booth
encoded technique is the most efficient among
all techniques as it reduces the number of
partial products by an aspect of two [2–8].
Radix-8 reduces the number of Partial
Products by an aspect of three as compared to
that in Radix-2, but the generation of partial
products in Radix-8 is a complex process. This
is so because with the increase in radix, the
number of multiples and also the hard
multiples increase [9]. Thus, Radix-8 and more
higher order radices are not cost effective and
are rarely used [10].
In a series of small length adder circuits are
used for producing hard multiples [11].
Further, compressor circuits or adder circuits
are employed to accumulate the partial
products for the addition purpose. For speedy
accumulation and addition of partial products,
fast multi operand adder circuits like Wallace
Tree and Carry Save Adder (CSA) are
incorporated in the architectures [12].
Investigation to various properties of RNS is
done in [13]. Also, it is also made clear that
residue code is expressed in terms of linear
congruencies. Design of Radix-4 and Radix-8
booth encoded multi modulus multipliers have
been proposed and a comparison of these
proposed multipliers was done with booth

13. JoVDTT (2016) 15-21 © STM Journals 2016. All Rights Reserved Page 15
Journal of VLSI Design Tools & Technology
ISSN: 2249-474X (online), ISSN: 2321-6492(print)
Volume 6, Issue 3
www.stmjournals.com
Design of FPGA Based ALU Using Reversible Logic Gates
Vishal A. Wankhede*, Ramprasad M. Gawande
1
Department of Electronics and Telecommunications, SNJB’s College of Engineering, Chandwad,
Nasik, Maharashtra, India
Abstract
Reversible or information misfortune less circuits has applications in computerized signal
handling, correspondence, PC design and nanotechnology. Reversible technique is utilized to
minimize heat that happens in traditional circuits by keeping the loss of data. This paper
proposes a reversible configuration of an ALU. This ALU comprises of eight operations, five
are of arithmetic category and three are from logical category operations. An arithmetic
operations incorporate add, sub, increase by one, decrement by one, multiply whereas logical
operations incorporate AND, OR, and XOR. Each module is being composed utilizing the
fundamental reversible basic gates. The Area analysis, power analysis and delay analysis of
the different sub modules is performed and a correlation with the conventional circuits is
likewise completed. We designed the ALU in Verilog HDL and Simulated by using Modelsim
6.4c Software. The proposed ALU Design is synthesized by Xilinx and Implemented into
FPGA Spartan 2 XC2S200PQ208.
Keywords: VLSI, quantum cost, ALUt, revesible gate, reversible logic
INTRODUCTION
Reversibility in calculating denotes that no
information about the computational states can
ever be lost, so we can recover any previous
stage by computing towards the back or un-
computing the results. This is known as logical
reversibility. The benefits of logical
reversibility can be achieved only after
employing physical reversibility. Physical
reversibility is a process, which dissipates zero
energy to hotness. Perfect physical
reversibility cannot be achieved practically.
Computing systems withdraw heat when
voltage levels change from high to low that is
bits from one to zero.
Most of the energy needed to make that
change is given off in the form of heat. Instead
of changing voltages to new levels, reversible
circuit elements will slowly move charge from
one node to the next. In this manner, one can
only supposed to lose a little amount of energy
on each change. Reversible computing
intensely affects digital logic designs.
Reversible logic fundamentals are needed to
recover the state of inputs from the outputs. It
will affect instruction sets and high-level
programming languages as well. Ultimately,
these will also have to be reversible to provide
peak efficiency. Landauer in 1961 expressed
that the circuits composed utilizing irreversible
components dissolve heat because of the loss
of data bits [1]. It is demonstrated that the loss
of one piece of data significances in
dissemination of K.T.log2 Joules of warmth
vitality where K is the Boltzmann's steady and
T is an Absolute temperature at which the
operation is performed. Bennett in 1973
expressed that this warmth dispersal because
of data misfortune can be gotten away if the
circuit is planned utilizing reversible Logic
Gates [2]. High-performance chips liberating
large amounts of heat inflict practical
limitation on how far can we improve the
performance of the system.
Reversible circuits that preserve information,
by un-computing bits instead of throwing them
away, will soon offer the only physically
possible way to keep increasing performance.
Reversible computing will also lead to
upgrading in energy efficiency. Energy
efficiency will fundamentally affect the
speediness of circuits such as Nano-circuits
and therefore the speed of most computing
applications. To raise the portability of devices

14. JoVDTT (2016) 22-27 © STM Journals 2016. All Rights Reserved Page 22
Journal of VLSI Design Tools & Technology
ISSN: 2249-474X (online), ISSN: 2321-6492(print)
Volume 6, Issue 3
www.stmjournals.com
Linearity Analysis of Traditional Single and Double
Balanced Down Conversion Mixers
Akash I. Mecwan*, N.M. Devashrayee
Department of Electronics and Communications, Institute of Technology, Nirma University,
Gujarat, India
Abstract
More sophisticated designs of communicating devices are required with tremendous scaling in
MOS. Mixers play a vital role in all radio transmitters and receivers. To improve the
sensitivity of the receivers, the low noise amplifiers are designed with very high gain. Higher
gain of amplifier saturates the preceding sections and forces them to operate in the nonlinear
region. MOS based Single Balanced and Double Balanced mixers are the most common
designs for down conversion mixer. The paper discusses the linearity issue for both the
traditional mixers. Basic definition of linearity is explained and the mathematical analysis
based on Taylor’s series expansion is carried out for single and double balanced mixers.
Keywords: Linearity, IIP3, mixer, mathematical analysis, amplifiers
INTRODUCTION
With improvement in the fabrication
processes, it is possible to scale the MOS
device to nano meter regime. With the
reduction in the device dimensions, the
linearity of the device suffers, which leads to
the requirement of more sophisticated circuit
topologies [1]. Down conversion mixer is an
important part of radio receiver, which is
preceded by Low Noise Amplifier (LNA).
Mixer receives two inputs, one from LNA,
which is called RF signal and second from the
local oscillator, which is called LO signal. The
output of the mixer is known as IF or
intermediate signal.
The most famous mixer topologies are single
balanced and double balanced mixer
topologies [2]. It is often said that the double
balanced mixers are more linear compared to
the single balanced one [3], but the
mathematical analysis for the said comparison
is not easily available anywhere. The paper
discusses the definition of linearity. The
mathematical analysis of linearity is presented
and the same is applied to the mixers using
Taylor’s series expansion.
The flow of the paper is as by presenting the
linearity and the mathematical formulas to find
the linearity of the design, discussing single
and double balance mixer theory, presenting
the linearity analysis of both the mixers.
Lastly, the results and discussion and lastly the
paper is concluded with remarks.
LINEARITY
MOS devices are transconductance devices.
The output current change with change in the
gate voltage. Due to nonlinear current–voltage
relation of MOS, there may be many unwanted
signals or harmonics observed in the final
output, which are not applied at the input. The
current voltage relation of MOS like device
can be expressed using Taylor’s series as:
𝑦(𝑡) = 𝑎1 𝑥(𝑡) + 𝑎2 𝑥(𝑡)2
+ 𝑎3 𝑥(𝑡)3
+ ⋯ (1)
Where, y(t) and x(t) are the input to and output
from the MOS device respectively and 𝑎1, 𝑎2
and 𝑎3 are the gain of respective terms. There
are various effects of nonlinearity as described
below.
Total Harmonic Distortion (THD)
If a sinusoid signal, 𝑥(𝑡) = 𝐴 cos 𝜔𝑡 is applied
at the input of the MOS device, the input–
output relation can be describe as shown
below after neglecting the higher order term.
𝑦(𝑡) = 𝑎1 𝐴 cos 𝜔𝑡 + 𝑎2 𝐴2
cos2
𝜔𝑡 +
𝑎3 𝐴3
cos3
𝜔𝑡 … (2)

15. JoVDTT (2016) 28-34 © STM Journals 2016. All Rights Reserved Page 28
Journal of VLSI Design Tools & Technology
ISSN: 2249-474X (online), ISSN: 2321-6492(print)
Volume 6, Issue 3
www.stmjournals.com
Development of System for Speech Enhancement using
Combinational Adaptive LMS on Reconfigurable
Platform
Pradip C. Bhaskar, Prachi S. Gosavi*
Department of Technology, Shivaji University, Kolhapur, Maharashtra, India
Abstract
Low cost and robustness makes the least mean square (LMS) algorithm most popular.
Improved adaptive filter performance can be obtained by combinational approach. In this
paper, for speech enhancement, we used one of such approaches known as ‘filter
combination’. As our simulation results show, Fixed-Sign LMS algorithm overcome other
algorithms in terms of SNR and mean square error.
Keywords: Adaptive filter, speech enhancement, windows, convex combination
INTRODUCTION
Speech is the common way to communicate
between the people. But such speech is
corrupted by various noises, which loses the
required information. So far, number of
algorithms is presented based on adaptive
filtering for speech enhancement. Adaptive
filtering can be defined as, for processing the
signals, filtering parameter changes according
to some criteria. Many types of adaptive filters
proposed to adjust the weights based on
different schemes. Among that, the least mean
Square (LMS) algorithm is the most common
algorithm used [1]. The powerful DSP along
with developed adaptive filtering algorithm are
having great numbers of application, such as
telecommunication, sonar, radar, audio
processing, where adaptive filtering technique
is successfully used. The design technique
used and algorithm of adaption leads to
changes in efficiency.
FPGA (Field Programmable Gate Array)
system gained its popularity over DSP in terms
of its reconfigurable hardware logic blocks
according with its usage and performance
results. The remainder of the paper is
organized as follows. Secondly, we presented
a background of adaptive filtering algorithm
and mathematical model of combinational
approach; followed by the implementation,
which is presented after the background. Then
the hardware simulation results are presented.
Lastly, the concluding remarks are given in
this approach.
BACKGROUND
Adaptive Filtering
An adaptive filter is a system whose transfer
function is controlled by various parameters
and adjustment those parameters is done
through optimization algorithm (Figure 1).
Many DSP applications require adaptive
filtering techniques for processing the
signals [2].
Fig. 1: Functional Diagram of Adaptive
Filter.
The LMS digital algorithm is based on the
gradient search according to following
equation:
𝑤 𝑛+1 = 𝑤 𝑛 + 𝜇 ∗ 𝑒 𝑛 . 𝑥 𝑛 (1)
Where,
𝑤 𝑛 = weights vector in moment n,
𝑤 𝑛+1 = weights vector in n+1,
x(n) = input signal which is to be filtered
e(n) = Error signal generated by taking
difference between filtered signal and desired
signal.

16. JoVDTT (2016) 35-44 © STM Journals 2016. All Rights Reserved Page 35
Journal of VLSI Design Tools & Technology
ISSN: 2249-474X (online), ISSN: 2321-6492(print)
Volume 6, Issue 3
www.stmjournals.com
Design of High-Speed and Low-Power Carry Skip Adder
Gutlapalli Venkatrao1,
*, Motkuri Krishna2
Department of Electronics and Communication Engineering,
Geethanjali College of Engineering and Technology, Hyderabad, Telangana, India
Abstract
In this brief, we present a high speed and lower power consumption carry skip adder (CSKA)
architecture compared with the conventional one. The increment of speed is attained by
implementing concatenation and incrementation strategy to improve the efficiency of the
conventional CSKA (Conv-CSKA) architecture. Instead of make use of multiplexer logic, the
proposed architecture makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI)
combination gates for the carry skip logic. The structure possibly designed with both fixed
stage size and variable stage size styles, wherein the latter further improves the speed and
power parameters of the adder. This expansion utilizes a modified parallel structure for
increasing the slack time, and enabling further voltage reduction. The proposed architectures
are evaluated by comparing their speed, power, and area with those of other adders using 90-
nm and 45-nm static CMOS technology.
Keywords: Carry skip adder (CSKA), high performance, incrementation, concatenation
INTRODUCTION
The key building blocks in arithmetic and
logic circuits are adders, which have the
capability to increase their speed and reduce
the power consumption. These factors affect
the processor’s speed and power consumption.
Many works have been done in order to
optimize the speed and power of these units
and their reports have been mentioned [1–4].
The designers of general purpose processors
have to take a challenge in order to achieve
higher speeds at low-power consumptions.
The power consumption of digital circuits can
be reduced by many methods but the most
effective technique is to reduce the supply
voltage due to the quadratic dependence of the
switching energy on the voltage. The main
leakage component in OFF devices is the sub-
threshold current, which has an exponential
dependence on the supply voltage level
through the drain-induced barrier lowering
effect. The ON devices operation may present
in the super- threshold, near-threshold, or sub-
threshold regions. When working in the super-
threshold region lower delay and higher
switching and leakage powers are produced
compared with near/sub-threshold regions.
The sub-threshold region consists of logic gate
delay and leakage power, which exhibit
exponential dependences on the supply and
threshold voltages. The circuit, which operates
in the sub-threshold region, causes a large
delay for the circuits with a small change in
the sub-threshold current.
A more suitable trade-off point, when
compared with the sub-threshold one, can be
provided between delay and power dissipation
in the near threshold region. This is because
the trade off point results in lower delay
compared with the sub-threshold region and
hence results in low switching and leakage
powers compared with the super-threshold
region. The supply voltage levels near-
threshold operation, i.e. near the threshold
voltage of transistors, when compared with the
sub-threshold region will have less process
and environmental variations.
The power and performance along with
dynamic voltage and frequency scaling which
depend on the supply voltage have become a
motivation for the design of circuits. These
circuits consists a system, which may change
the voltage and frequency of the circuit in
order to reduce the energy consumption.
Along with the knob of the supply voltage,
different adder structures/families can be
chosen for speed/power optimization. The
delay, power consumption, and area usage will
be different for different adder families.

17. JoVDTT (2016) 45-55 © STM Journals 2016. All Rights Reserved Page 45
Journal of VLSI Design Tools & Technology
ISSN: 2249-474X (online), ISSN: 2321-6492(print)
Volume 6, Issue 3
www.stmjournals.com
A Unified Ultra-Low Power Architecture of Probabilistic
Adder Based on GDI Technique
Srinibasa Padhy, B.S. Patro*, Monica Swain, J.K. Das
VLSI Design and Embedded System, School of Electronics, KIIT University,
Bhubaneswar, Odisha, India
Abstract
In the present arena of technology scaling, the power consumption in the deep submicron
technology plays a pivotal role as the transistor counts increases dramatically. Therefore, the
need of the hour is to focus on power dissipation. The rate of occurrences of errors in the
present VLSI scenarios has become higher and inevitable, and is increasing along with
technology scaling. Eradicating all the errors is a cumbersome task; still a semi accurate
result in better performance instead of accurate one can be accepted in some specific
applications. An error tolerance adder is one such application specific adder to overcome the
power delay trade-off by eradicating carry propagation and introducing a little error. To
further enhance its efficiency and performance, GDI technique is introduced. In this paper,
the GDI based architecture of probabilistic error tolerant adder (III) has been introduced,
thus inferring the simulation with much more reduced power, delay and enormously enhanced
performance over conventional adder.
Keywords: Error tolerance, gate diffusion input, full adder
INTRODUCTION
In conventional digital VLSI design, it is
always preferable to get accurate results and
perfect functioning of the circuit, but at the
same time in non-digital world these ideal
operation can be compromised. Analog
computation, which yields “semi-accurate”
results in place of ideal result, can be accepted
with a better performance [1–3].
Among one of such application is a
communication system where in the front end
the basic signal is sampled before being
converted into digital signal where in the back
end the digital signal is processed and
transmitted through a channel which is noisy
and then converted back to an analog signal. A
circuit with such an application is said to be
error-tolerant. It is most probable that the error
will appear during the whole process.
A circuit is said to be error tolerant if:
 It has defects that results in internal as
well as external errors
 The systems implementing this circuit
yield acceptable results
Nowadays to combat the issues like lower-cost
parts improved revenues, these error tolerant
circuits are being used. Since it is an
application specific circuit some of its
application lies with image and sound
processing, with the trending tradeoff between
power and speed it is getting difficult to
overcome this problem. A third parameter
comes into existence called “accuracy”. It has
been found that relaxing the requirement of
accuracy, manufacturing cost, verification
cost, power consumption and delay can be
drastically reduced without much hampering
the circuit performance. With such an
application, an error tolerant adder has been
designed and described which makes it easy to
decipher the calculated values without
affecting its performance. The proposed paper
is an enhancement of error tolerant adder
ETA-III, which is based on GDI technique [4–
6]. ETA can be used in various applications
such as human sensory system’s touch, smell,
image, sound that are always error tolerant [7].
It can be useful to some of the digital signal
processing systems that include images
processing and speech processing.

18. JoVDTT (2016) 56-70 © STM Journals 2016. All Rights Reserved Page 56
Journal of VLSI Design Tools & Technology
ISSN: 2249-474X (online), ISSN: 2321-6492(print)
Volume 6, Issue 3
www.stmjournals.com
Survey of System-on-Chip Modular Test Approach
Harpreet Vohra1,
*, Amardeep Singh2
1
Department of Electronics and Communication Engineering, Thapar University,
Patiala, Punjab, India
2
Department of Computer Science and Engineering, Punjabi University, Patiala, Punjab, India
Abstract
The advancement in semiconductor technology over the past few decades has enabled the
industry to develop new design and reuse methodologies referred as System-on-chip (SoC)
design. These typically integrate heterogeneous mix of various complex analog and digital
cores, with all their necessary electronic circuitry. The recent advancements have led to the
use of the 3D structures (3D-SOCs) that brought along the benefits of higher performance,
minimum average interconnect length, reduced power and smaller footprint. These
revolutions have not only brought in new issues of design but also their testing which is
becoming the major bottleneck in determining the overall system cost and a defect free
delivery to market in time. To facilitate the testing of cores lying inside such complex SOCs
modular approach, concurrency in test application are the only viable ways. However these
come at their own costs of constraints like power, test bandwidth, resources like “through
silicon vias”, BIST etc. This paper first discusses in general the various challenges in testing
of core-based system chips, the associated test factors and modular test approach. It is further
followed up by the various ways of addressing the challenges and the corresponding research
areas.
Keywords: System on chip test, test data compression, test access architecture, embedded core
based design, system on chip test architecture
INTRODUCTION
To cater to the ever-growing demands of the
consumer market, the VLSI industry is being
forced to add more and more complexity on
chip. The achievement of the remarkably high
level of integration has been made possible
due to the corresponding advancements in the
semiconductor industry. Due to this, it is now
common to find complete systems-on-chip
(SOC) consisting of a mix of analog/ digital
blocks in the form of integration of predefined
and pre verified embedded cores. Embedded
core based design approach on one hand saves
the design cost while on the other it leads to a
strong benefit of getting the various IP blocks
from the vendors who are stalwarts in their
respective domains. These IP cores can be in
the form of a synthesizable HDL code, a gate
level netlist or a layout description of a circuit.
It has been observed that though
miniaturization in the component sizes has
been achieved however, the interconnects have
not scaled down at the same pace at the global
level and even if they have been at the local
interconnect level, the R-L-C component have
led to performance issues [1]. To cope up with
the demand for higher integration 3D SOC [2]
has started to gain considerable attention that
allows growth in the vertical dimension. Big
designs with smaller foot prints can be
obtained by stacking multiple dies together.
The ITRS roadmap predicts 3D integration as
a key technique to overcome this so-called
“wiring crisis” [3]. 3D ICs employs through
silicon via (TSV) for the interconnectivity.
This fast growing advancement in the
technology has led to the challenges for the
design engineer and a more complicated and
expensive problem for test engineers.
The importance of reducing the cost of test is
further motivated by comparing the test cost
with the cost of fabrication. Today, the cost of
test is a significant part of the overall
manufacturing cost (including the cost of
fabrication and the cost of test). All this makes
it mandatory to have a good and reliable

19. JoVDTT (2016) 71-87 © STM Journals 2016. All Rights Reserved Page 71
Journal of VLSI Design Tools & Technology
ISSN: 2249-474X (online), ISSN: 2321-6492(print)
Volume 6, Issue 3
www.stmjournals.com
Design of Low Power Resistor Less Flash ADC for UWB
Receiver Applications
Ankush Chunn*, Rakesh Kumar Sarin
Department of VLSI Design, Dr. B. R. Ambedkar National Institute of Technology,
Jalandhar, Punjab, India
Abstract
In this paper, two designs of flash analog to digital converters (ADCs) based on threshold
inverter quantization (TIQ) technique are presented. The parallel threshold inverter
quantization (PTIQ) flash ADC exploits the advantage of reduction in capacitance and power
consumption if the transistors are placed in parallel. Another design called low voltage
tunable body bias (LVTBB) PTIQ ADC operates at near threshold voltage level to minimize
the power consumption. The PTIQ and LVTBB ADC designs attain figure of merit of 0.09625
pico Joule/conversion (pJ/conv) and 0.06 pJ/conv respectively which is comparable to the
existing state of art ADCs.
Keywords: ADC, TIQ, PTIQ, LVTBB, threshold voltage, power consumption
INTRODUCTION
Ultra-wideband (UWB) was deregulated for
commercial purpose in short-range
communications by the Federal
Communications Commission (FCC) in 2002.
It hosts several applications between 3.1 GHz
to 10.6 GHz. Since then it has emerged as an
attractive solution for wireless communication,
networking and GPS [1]. However, the design
of UWB poses many challenges, one of which
is sampling and digitization of high frequency
signals. In spite of high sampling rate
requirement, the resolution requirement for
ADC is bit relaxed in case of UWB.
Specifically, there is minimal improvement for
an ADC with resolution of more than 4 bits
than a 4-bit ADC in case of UWB receivers
[2–4]. So, 4-bit flash ADC architecture is
suitably chosen for the implementation
purpose.
ADC is an essential device required in
between analog and digital interface. With the
exponential growth in wireless domain, there
is need of more power efficient ADCs to be
able to strive out for faster and low power
consuming applications. For this, low power
techniques are being explored to satisfy the
unending demand and this is pushing the
ADCs to their fundamental limits to be
integrated in system-on-chip (SOC)
applications. Several techniques such as
comparator offset cancellation, capacitive
interpolation, averaging and folding [5] have
been used in literature to bring down the
power consumption. These techniques not
only improve the power dissipation but also
along with bring the linearity of ADCs.
However, these techniques need extra circuitry
to be accommodated with other digital circuits
on the chip which causes the SOC integration
problem in ADCs. In literature, the SOC
integration problem has been addressed in [6],
where authors used inverter as comparator to
design a flash ADC without using any resistor
network.
The latch based comparators are replaced by
inverters that have set threshold voltage to be
used as reference voltage as in comparator.
This so-called threshold inverter quantization
(TIQ) technique is based on internal reference
generation using the voltage transfer
characteristic (VTC). Another power and
resolution adaptive (PRA) ADC based on TIQ
is published in [7] which allows power
reduction if the resolution of ADC is varied
linearly. Another ADC based on quantum
voltage comparator using TIQ technique is
implemented in [8] with the improvement in
linearity of ADC. Similar ADCs based on TIQ
technique has been presented in [9] at lower

20. JoVDTT (2016) 88-93 © STM Journals 2016. All Rights Reserved Page 88
Journal of VLSI Design Tools & Technology
ISSN: 2249-474X (online), ISSN: 2321-6492(print)
Volume 6, Issue 3
www.stmjournals.com
VHDL Implementation of Network-on-Chip
Router using Round Robin Arbiter
Minakshi M. Wanjari1,
*, Pankaj Agrawal2
, Ravindra Kshirsagar3
1
Department of Electronics Engineering, Priyadarshini College of Engineering, Rashtrasant Tukadoji
Maharaj Nagpur University, Maharashtra, India
2
Department of Electronics and Communication Engineering, G.H. Raisoni Academy of Engineering
and Technology, Rashtrasant Tukadoji Maharaj Nagpur University, Maharashtra, India
3
Department of Electronics Engineering, Priyadarshini Indira Gandhi College of Engineering,
Rashtrasant Tukadoji Maharaj Nagpur, University, Maharashtra, India
Abstract
As the technology progresses, a large number of devices can be incorporated into a single
chip. So, the communication between these devices becomes critical. The network-on-chip
(NoC) is a technology used for such communication and overcomes the constraints of
traditional bus-based system-on-chip (SoC). Router is the backbone of NoC and determines
the performance to a great extent. This paper focuses on the implementation of five port
virtual channel router which is considered as promising router architecture for NoC. The
major building blocks of router are virtual channel buffer architecture, fairness arbiter, i.e.
RRA and a crossbar switch. An arbiter employs a scheduling algorithm which is used to
decide which one of several requests would be serviced. The round robin arbiter is based on
the assignment of a fixed time slot per requester. The source code is written in VHDL. The
proposed router is synthesized and simulated in Xilinx ISE Design Suite 13.1.
Keywords: Network-on-chip (NoC), system-on-chip (SoC), intellectual property (IP),
processing element (PE), network interface (NI), virtual channel (VC), round robin arbiter
(RRA)
INTRODUCTION
Nanoscale technology allows integration of
millions of transistors on a single chip. As the
integration goes on increasing, it aggravates
the design productivity gap and timing closure
problems. A system on chip is an integrated
circuit that incorporates all components of
electronic system into a single chip. In SoC,
system bus is used to connect several
functional units; hence, the communication
capacity is up to gigabits. Due to the fixed
scalability of system bus, it cannot meet the
requirement of current SoC implementations
and so, communication between these devices
becomes critical. On chip physical
interconnections will present a restricting
factor for performance and energy
consumption [1]. NoC is new method to
design the communication subsystem between
intellectual property cores in a system on chip.
NoC is aimed to solve the shortcomings of
these, by implementing a communication
network of switches/micro-routers and
resources. It is widely said that NoC will
become the mainstream of SoC design
methodology [2–4]. Router is the key
component of NoC and does the important
task of leading and organizing the data flow.
Router architecture determines the
performance of network-on-chip to a major
extent, and virtual-channel router is called as
the promising choice for NoC [5]. This paper
consists of the remaining sections as: next, the
network-on-chip background is presented
followed by the network-on-chip architecture,
the proposed efficient NoC router, the
implementation and results of the design and
the last section is conclusion.
NETWORK-ON-CHIP: BACKGROUND
The communication system between processing
elements in SoC is the NoC. Links of the
network-on-chip consist of wires and these are
shared by many signals. The links in the NoC

21. Journal of
VLSI Design Tools
& Technology
(JoVDTT)
ISSN 2249-474X(Online)
ISSN 2321- 6492 (Print)
September–December 2016
SJIF: 3.913
Index Copernicus Value : 45.28
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