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ADCS in ASICs
- 1. ADCs in ASICs An Overview for System Designers Dr. Mike Coulson 28/05/2015 Swindon Template Slides 01 1
- 2. Presentation Contents 28/05/2015 Swindon Template Slides 01 2 Introduction The Benefits of an Integrated ADC Essential Terminology for Describing ADCs Types of ADC The Challenges of Integration To Integrate or Not? Questions
- 3. Embedded sensor systems are typically mixed signal designs Introduction 28/05/2015 Swindon Template Slides 01 3 Analog side From transducer To main system Analog Digital
- 4. An ASIC is most useful when it contains the ADC too Introduction 28/05/2015 Swindon Template Slides 01 4 Analog sideAnalog Digital
- 5. Basic specifications Conversion rate Resolution Static Performance Measures DNL INL Essential Terminology for Describing ADCs 28/05/2015 Swindon Template Slides 01 5
- 6. Basic specifications Conversion rate Resolution Static Performance Measures DNL INL Essential Terminology for Describing ADCs 28/05/2015 Swindon Template Slides 01 6
- 7. Basic specifications Conversion rate Resolution Static Performance Measures DNL INL Which metric matters? Absolute error − INL Error in adjacent codes − DNL Essential Terminology for Describing ADCs 28/05/2015 Swindon Template Slides 01 7
- 8. Dynamic Performance Measures Reflect static & dynamic errors Can be measured by FFT SNR − Fundamental limit THD − Just harmonic power SINAD − Both noise and harmonics ENOB Essential Terminology for Describing ADCs 28/05/2015 Swindon Template Slides 01 8 𝑆𝑁𝑅 (𝑑𝐵) = 6.02 𝑁 + 1.76
- 9. Many different architectures exist We will discuss four of the most important Difficult to quote absolute resolution and bandwidth Types of ADC 28/05/2015 Swindon Template Slides 01 9
- 10. Flash ADCs Highest speeds Large (approx. 2N comparators), so constrained to low resolutions (8 bit) Power hungry Types of ADC : Flash 28/05/2015 Swindon Template Slides 01 10
- 11. Pipeline ADCs Each sample passes through a series of stages, like a production line Each stage adds further precision to the result, but also adds further ‘pipeline delay’ High speed, but high power Popular for 8-14 bit applications Types of ADC : Pipeline 28/05/2015 Swindon Template Slides 01 11
- 12. Successive Approximation (SAR) ADCs SAR logic attempts to recreate input with an internal DAC Several clock cycles per conversion, as different codes are tried Popular for moderate speed applications, in the 8-14 bit range Can be very power efficient Types of ADC : SAR 28/05/2015 Swindon Template Slides 01 12
- 13. Sigma Delta ADCs Type of oversampling Popular in audio applications Low speed High resolution (16-18 bit) Care required in design Types of ADC : Sigma Delta 28/05/2015 Swindon Template Slides 01 13
- 14. Interference Digital and analog circuits are poor neighbours on an ASIC… Interference via shared power supplies Interference via shared silicon substrate The Challenges of Integration 28/05/2015 Swindon Template Slides 01 14
- 15. Small geometry processes may be required to suit digital portions of the ASIC But analog performance may be compromised… for example: Low supply voltages (to suit digital parts) − These limit signal swings within the chip − Robust design is more difficult (process, temperature, ageing) − So partition into multiple supply domains, or use special circuit architectures Capacitor, resistor and transistor matching − Mismatch introduces INL and DNL − So employ digital error correction and calibration Success comes down to experience, and having a portfolio of proven circuits The Challenges of Integration 28/05/2015 Swindon Template Slides 01 15
- 16. Not appropriate To Integrate or Not? 28/05/2015 Swindon Template Slides 01 16 Where ADC performance is crucial requiring a specialized fabrication process Highly beneficial Most automotive & industrial systems e.g. process monitoring & control When size or power is critical e.g. hearing aids, medical implants When cost is absolutely critical so a mixed signal ASIC is the only option
- 17. Any Questions? 28/05/2015 Swindon Template Slides 01 17
- 18. Thank you 28/05/2015 Swindon Template Slides 01 18
Notes de l'éditeur
- Mike Coulson – design engineer at Swindon Silicon Systems in England. We design “Application Specific ICs” (ASICs). My talk today concerns the growing use of analogue to digital converters (ADCs) within application specific ICs. It is intended as a briefing for system designers who may opt to go down this advantageous route.
- I will start with some further words of introduction about sensor systems and ASICs… and why you would want to integrate an ADC within an ASIC Then, because the ASIC design process is always a dialogue between the ASIC designer and their customer, I will explain some essential ADC concepts that may come in useful, including some key terminology and some common circuit architectures. I will also describe some of the challenges that chip designers face when building ADCs within ASICs. With this in mind, I can address the question: when is it appropriate to integrate an ADC , and when is it not?
- Embedded sensor systems are often mixed signal designs, where an analogue input from a transducer (such as a voltage, or a current) is preconditioned, digitized by an ADC [circle ADC], and then subject to processing in the digital domain. An ASIC is a custom designed silicon chip, which replaces numerous discrete components on a PCB. The conventional ASIC solution would look like this [reveal ASIC board]. The analog functionality has been absorbed into an analog ASIC, and the digital functionality has been absorbed into a digital ASIC. The ASIC solution is desirable because it is [reveal Cheap, small, robust] cheap, small and robust, having fewer parts to purchase, test and assemble.
- But an ASIC is most useful when it contains the ADC too. This allows both the analogue and digital chips to be absorbed into the same package. [Reveal single chip solution]. Taken to the extreme, you end up with your entire signal chain sitting within a single chip. Now this is hugely advantageous. First, the benefits of cost, size and robustness are even more pronounced. But having an integrated ADC is also [reveal flexible] more flexible, because the chip designer isn’t restricted to choosing an ‘off the shelf’ ADC, and can instead optimise the circuit for the task in hand. It is also [reveal more convenient] more convenient, because the entire signal path comes under the care of the ASIC supplier, and the customer receives a complete, fully production-tested solution to drop into their product. Although highly beneficial, ADC integration isn’t trivial, and the ASIC designer must work closely with the customer throughout. For this reason, it’s important that the customer – the system level designer - should be familiar with how ADCs are specified. So I’ll now cover some essential ADC background.
- We’ll start with essential terminology for describing ADCs. At the simplest level, an ADC is specified in terms of conversion rate and resolution. The conversion rate is perhaps self explanatory: the number of times the ADC can digitise its analogue input, each second. The resolution (often given as the number of bits in the output) describes the number of different levels that the ADC can represent. [Reveal transfer function] These output levels are called output codes. When you plot the output code against the input voltage, you obtain the ‘transfer function’. The transfer function is described by the code transition voltages. For an ideal, linear transfer function the code transition voltages are evenly spaced. This means that the input voltage range over which each output code is produced (termed the code width) is equal for every code. [Reveal static performance measures] This brings us onto ‘static performance measures’, which describe deviations of the real transfer function from the perfectly linear case, and which are measured under DC inputs.
- We now look at a non-linear transfer characteristic The code transition voltages are not uniformly spaced This means that some codes are ‘narrow’ (persisting over a smaller input range), and some codes are ‘wide’. The code width error is termed the ‘DNL’. We typically specify the maximum DNL encountered across the whole input range. Now you can perhaps see that error in a given code transition voltage will be the sum of all preceding code width errors. For example, if the first 100 codes are all 1% too wide, the 100th code transition will occur a full code width higher than expected. This cumulative sum of the DNL is termed the Integral Non-Linearity (or ‘INL’). We typically specify the maximum INL encountered across the whole input range.
- As this graph shows, a higher resolution converter could have a small peak DNL, yet its INL may grow to a large value over hundreds of codes. ****** In some applications, the INL matters, in others the DNL is more important. For example, if we have a temperature sensor that measures an absolute value, the maximum INL might be of concern. But if we measure a rate of change, exciting each code in sequence, the maximum DNL might be more critical. So the application must always be properly understood when choosing an ADC.
- We then have ‘dynamic performance measures’, which describe output signal purity under a full scale sinusoidal input, shown by the dotted line. They are typically measured by taking an FFT of the output. Dynamic performance is always worse than static performance, as it reflects dynamic errors such as the incomplete charging of capacitors, and the finite bandwidth of amplifiers. The first dynamic performance measure is the signal to noise ratio (SNR), which describes general noise and interference in the ADC’s output The SNR is fundamentally limited by the ‘quantisation error’ that is always present between the input and it’s digitised representation. A classic equation relates the SNR limit to the converter resolution. Unsurprisingly, when the resolution is increased, the quantisation errors become smaller, and the SNR limit is improved. (The equation makes sense: it says that for each extra bit of resolution, which will halve the quantisation error, the noise power will fall by 6dB which is the expected factor of 4). ******* The THD is the Total Harmonic Distortion, and represents only harmonic power in the output spectrum. It is particularly important for audio applications. ******* The SINAD measures both noise and harmonics, so gives a measure of overall signal purity. ******* Finally, the ENOB is an intuitive way of describing the SINAD. It is the resolution of a perfect converter that has the same noise and distortion as the real one under test. So you may find a 16-bit ADC that seems perfect for your application, but which starts to look less attractive when you discover it has an ENOB of 12.
- Difficult to quote absolute resolution and bandwidth, because these are so process dependent. we’ll choose cheapest process we can, to maximise savings for customer process choice may be a compromise to suit analog and digital aspects of the ASIC
- We will start with flash ADCs, which are the fastest but also the largest and most power hungry. They are large because they consist of a large bank of comparators, each fed with a staggered reference voltage from a resistor ladder. Each comparator simultaneously compares the input voltage with its own reference, explaining both the high speed and high power consumption. Flash ADCs are reserved for the highest speed applications, such as communications systems.
- Pipeline delay may cause instability in closed-loop control systems.
- Sigma Delta ADCs employ a form of oversampling. In oversampling, many noisy low resolution conversions are averaged to obtain a single high resolution result. This is usually taken to the extreme, where the low resolution conversion results are 1-bit. The output is then a random PWM signal. The random PWM signal is then digitally averaged (that is, passed through a filter) to remove high frequencies, and recover a high resolution result.
- Digital circuitry is noisy: it draws current from the power rail at high frequency, and dumps it to the ground. This disturbs not only the power supplies, but the voltage of the silicon substrate, in which the analogue circuits are built.
- Low supply voltages - Limited signal swings: signals can’t exceed the power supply voltages, and in many circuits can’t be allowed to approach them - Robustness to variations in the fabrication process, variations in temperature, and variations as the chip ages requires voltage margins… but with low supply voltages, you have little margin to play with Solution - This is a well known problem, and there are clever circuit architectures that can help. - Some processes provide both high voltage and low voltage transistors, so you can partition the chip into multiple supply domains, if you can tolerate the complexity & extra pins. Poorer matching – multiple supply domains and device geometries are an option. (High leakage currents – architectural solutions such as digital error correction exist to counter this kind of effect) This is where experience counts: in truth, a lot of these solutions come down to experience of what works and what doesn’t, and if you’ve done a lot of this kind of integration you build up a porfolio so as you want an ASIC supplier who has previously run into these problems and has a library of optimised circuit blocks to draw elements from.
- The primary reasons to integrate an ADC are reduction of cost and size. So we’d normally do this on a absolute budget, using the cheapest process options, to maximise the customer’s return. For this reason, an integrated ADC is unlikely to match the performance of a cutting edge discrete. So where ADC performance is crucial, requiring a specialized fabrication process, integration is probably not appropriate. However, a mixed signal ASIC brings considerable benefits in the vast majority of cases.