1. CURRICULUM VITAE
Sai Kumar Gurram
DFT Engineer
Soctronics Technologies Pvt. Ltd Mobile: +91 9676079939
Hyderabad. E-Mail: gsaikumar481@gmail.com
Objective
A motivated and enthusiastic DFT engineer with 3 year experience, having strong
understanding of design issues, seeking a design methodology role with scope for technical
challenges, career progression and possibly customer interaction.
Executive summary
• Worked for 2.11 years(November-2012 to till date) as DFT engineer in SoCtronics Technologies Pvt.
Ltd.
• Worked on 6 SOC projects.
• 3 projects successful tape outs.
• Technology Nodes worked on : 40nm , 28nm, 14nm and 22FDSOA.
• Role: Scan Insertion, Compression Insertion, Scan ATPG, TFT, Pattern Generation, Simulations,
Tester Support, MBIST, BSCAN(1149.1 and 1149.6), LVBSCAN flow with Mentor tools. Generation
of DFT libraries(scanModels and mdt) for technology libraries using Mentor tools.
• Have knowledge on PERL, TCL and SHELL scripting.
o Worked for porting projects from TSMC to GF.
Tools
• Metor Graphics(DFT)
• NC-Verilog
• Prime-Time
• Cadence Conformal LEC

2. Projects
Project#1
Organization : Soctronics Technologies Pvt Ltd.
Client : Ineda Systems
Technology : TSMC 40nm and GF28nm
Role
 Responsible for MBIST Insertion for blocks and SOC level. Responsible for BSCAN Insertion at SOC
level.
 Responsible for Scan Insertion, Compression Insertion and ATPG for block level and at SOC level.
 MBIST simulations both on RTL and Netlist at different stages (Golden RTL, Synth Netlist, Place
Opt., Route Opt. & ECO'ed netlists) & debugging them if they fail.
 Pattern Generation and Pattern Simulations for stuck-at and TFT for blocks.
 Responsible for Block level timing constraints (SDC's) for Scan-Shift and Scan-Capture through SDC
constraints team for Back end implementation.
 Responsible for Logical Equivalency Check at different stages.
 Responsible for DFT Automation flow through PERL and SHELL scripting.
Project#2
Client : Invecas
Technology : GF14nm
Role
• Responsible for BSCAN Insertion and PLL BIST Insertion at SOC level .
• Responsible for timing constraints (SDC's) for SYNTH and PD team for Back end implementation.
• Pattern Generation from SOC level .
• Simulations are done at zero delays, unit delays and using sdf annotations on final GDS netlists.
• Generating vectors at wafer level and for ATE.

3. • Responsible for Logical Equivalency Check at different stages.
Project#3
Client : Invecas
Technology : GF14nm
Role
• Scan & Compression logic insertion and stuck-At ATPG for Block level.
• Scan & Compression logic for glue logic at full chip level.
• Full chip & block level pattern generation & DFT verification.
• Interaction with Designers regarding issues seen.
• Responsible for Block and Full chip level timing constraints (SDC's) for Scan-Shift and Scan-capture
through SDC constraints team for Back end implementation.
• Coverage improvement analysis.
• Scan vectors generation and validation with zero delays & with delays(SDF Annotations).
• ECO's if required.
• Responsible for Logical Equivalency Check at different stages.
Project#4
Client : Invecas
Technology : GF14nm
Role
• Generated Automation flow for BIST and BSCAN Insertion using PERL and SHELL scripting.
• Responsible for BSCAN Insertion at SOC level .

4. • Responsible for connections of Internal Data Registers to TAP logic at SOC level.
• Responsible for timing constraints (SDC's) for SYNTH and PD team for Back end implementation.
• Pattern Generation from SOC level .
• Simulations are done at zero delays, unit delays and using sdf annotations on final GDS netlists.
• Generating vectors at wafer level and for ATE.
• Responsible for Logical Equivalency Check at different stages.
Project#5
Client : Invecas
Technology : GF14nm
Role
• Responsible for BSCAN Insertion at SOC level . Responsible for NAND TREE Insertion for pads.
• Responsible for connections of Internal Data Registers to TAP logic at SOC level.
• Scan insertion for glue logic at chip level and ATPG for Chip level for struck At .
• Responsible for timing constraints (SDC's) for SYNTH and PD team for Back end implementation for
BSCAN, Scan shift and Scan Capture.
• Coverage Improvement Analysis.
• Pattern Generation from SOC level .
• Simulations are done at zero delays, unit delays and using sdf annotations on final GDS netlists.
• Responsible for Logical Equivalency Check at different stages.
Project#6
Client : Invecas
Technology : GF22FDSOA
Role

5. • Responsible for BSCAN Insertion at SOC level . Responsible for NAND TREE Insertion for pads.
• Responsible for connections of Internal Data Registers to TAP logic at SOC level.
• Scan insertion for glue logic at chip level and ATPG for Chip level for struck At .
• Responsible for timing constraints (SDC's) for SYNTH and PD team for Back end implementation for
BSCAN, Scan shift and Scan Capture.
• Coverage Improvement Analysis.
• Pattern Generation from SOC level .
• Simulations are done at zero delays, unit delays and using sdf annotations on final GDS netlists.
• Responsible for Logical Equivalency Check at different stages.
Educational Qualifications
• May-2012-Nov-2012 - Diploma in VLSI – Logic Design – VEDAIIT, Hyd.
• 2008-2012- B.Tech (ELectronics and Communication Engineering) – Aurora’s Engineering College,
Bhongir, Nalgonda Dist..
Personal details
Date of Birth : 18th
March 1991
Marital Status : Unmarried
Nationality : Indian
Languages : Telugu, Hindi& English
Declaration
I Sai Kumar Gurram, hereby declaring that the above mentioned information is all true to best
of my knowledge and belief.

6. • Responsible for BSCAN Insertion at SOC level . Responsible for NAND TREE Insertion for pads.
• Responsible for connections of Internal Data Registers to TAP logic at SOC level.
• Scan insertion for glue logic at chip level and ATPG for Chip level for struck At .
• Responsible for timing constraints (SDC's) for SYNTH and PD team for Back end implementation for
BSCAN, Scan shift and Scan Capture.
• Coverage Improvement Analysis.
• Pattern Generation from SOC level .
• Simulations are done at zero delays, unit delays and using sdf annotations on final GDS netlists.
• Responsible for Logical Equivalency Check at different stages.
Educational Qualifications
• May-2012-Nov-2012 - Diploma in VLSI – Logic Design – VEDAIIT, Hyd.
• 2008-2012- B.Tech (ELectronics and Communication Engineering) – Aurora’s Engineering College,
Bhongir, Nalgonda Dist..
Personal details
Date of Birth : 18th
March 1991
Marital Status : Unmarried
Nationality : Indian
Languages : Telugu, Hindi& English
Declaration
I Sai Kumar Gurram, hereby declaring that the above mentioned information is all true to best
of my knowledge and belief.