Shunji Nishimura

10 Abonné

formal verification computer hardware theorem prooving theorem proving formal method hardware description category theory state machine agda soft constraints encodings at-most-k sat dependent types causal functions sequential circuits modern learners markup language digital material blackboard writing lecture education api classroom line synchronous circuits 機能モデル同期概念同期回路 multi-clock synchronous circuit 様相論理形式検証非同期回路 timing constraint asynchronous circuit multi-clock modal logic formal methods theorem proo functional programming

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Shunji Nishimura

Présentations

Agdaで回路設計（をしたい）

関数型言語と定理証明

同期回路-ステート・マシン対応の一般化

様相論理によるマルチクロック同期回路の形式検証体系

タイミング制約を含んだ回路記述方式とその意味論

定理証明言語によるハードウェア検証

Generalized Isomorphism between Synchronous Circuits and State Machines

多重様相論理による遅延依存非同期回路の形式検証体系

Theorem-proving Verification of Multi-clock Synchronous Circuits on Multimodal Logic

同期回路の機能的定義による同期概念の形式化

Broad-sense Synchronous Circuits on Partially Ordered Time

Stateless Circuit Model toward a Theorem-proving Hardware Description Language

LINE Messaging APIを用いた授業中のクイズ形式問題演習

Typing during Lectures as an Alternative for Blackboard Writing

Classification of Sequential Circuits as Causal Functions

Approximate-At-Most-k Encoding of SAT for Soft Constraints

J’aime

Proof summit 2017 for slideshare

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