1. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Device Modeling Report
Bee Technologies Inc.
COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT
PART NUMBER : TC74AC244FT
MANUFACTURER : TOSHIBA

2. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND 2A1
1Y4
2A2
1Y3
2A3
1Y2
2A4
1Y1
2G
VCC
_ U1
74AC244
SPICE MODEL
*$
*PART NUMBER : TC74AC244FT
*MANUFACTURER : TOSHIBA
*OCTAL BUS BUFFER, NON-INVERTED, 3-STATE OUTPUTS
*All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
.subckt 74ac244 1GBAR 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 DGND
+ 2A1 1Y4 2A2 1Y3 2A3 1Y2 2A4 1Y1 2GBAR DPWR
+ params: MNTYMXDLY=0 IO_LEVEL=0
UAB inva(2) DPWR DGND
+ 1GBAR 2GBAR OE1 OE2
+ D0_GATE IO_AC244 IO_LEVEL={IO_LEVEL}
U1 buf3a(4) DPWR DGND
+ 1A1 1A2 1A3 1A4 OE1 1Y1 1Y2 1Y3 1Y4
+ D_AC244 IO_AC244 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
U2 buf3a(4) DPWR DGND
+ 2A1 2A2 2A3 2A4 OE2 2Y1 2Y2 2Y3 2Y4
+ D_AC244 IO_AC244 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
.ends
.model D_AC244 utgate (
+ tplhmn=1ns tplhty=4.2ns tplhmx=7.5ns
+ tphlmn=1ns tphlty=4.4ns tphlmx=7.5ns
+ tpzhmn=1ns tpzhty=4.9ns tpzhmx=8.7ns
+ tpzlmn=1ns tpzlty=5.0ns tpzlmx=8.7ns
+ tphzmn=1ns tphzty=3.7ns tphzmx=7.9ns
+ tplzmn=1ns tplzty=3.7ns tplzmx=7.9ns
+ )
.model D0_GATE ugate ()
.model IO_AC244 uio (
+ drvh=24.5 drvl=18.7

3. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
+ inld=5pF
+ AtoD1="AtoD_AC244" AtoD2="AtoD_AC244_NX"
+ AtoD3="AtoD_AC244" AtoD4="AtoD_AC244_NX"
+ DtoA1="DtoA_AC244" DtoA2="DtoA_AC244"
+ DtoA3="DtoA_AC244" DtoA4="DtoA_AC244"
+ tswhl1=477ps tswlh1=470ps
+ tswhl2=477ps tswlh2=470ps
+ tswhl3=477ps tswlh3=470ps
+ tswhl4=477ps tswlh4=470ps
+ DIGPOWER="DIGIFPWR"
+ )
.subckt AtoD_AC244 A D DPWR DGND
+ params: CAPACITANCE=0
X1 DGND A 74AC_CLAMP
X2 A DPWR 74AC_CLAMP
C1 A DGND {CAPACITANCE+0.01pF}
ENORM NORM DGND VALUE={V(A,DGND)/(V(DPWR,DGND)+1U)}
O0 NORM DGND DO74AC244 DGTLNET=D IO_AC244
.ends
.subckt AtoD_AC244_NX A D DPWR DGND
+ params: CAPACITANCE=0
X1 DGND A 74AC_CLAMP
X2 A DPWR 74AC_CLAMP
C1 A DGND {CAPACITANCE+0.01pF}
ENORM NORM DGND VALUE={V(A,DGND)/(V(DPWR,DGND)+1U)}
O0 NORM DGND DO74AC244_NX DGTLNET=D IO_AC244
.ends
.subckt DtoA_AC244 D A DPWR DGND
+ params: DRVL=0 DRVH=0 CAPACITANCE=0
G_OH DPWR DPWR_OH
+ TABLE { V(DPWR_OH,DPWR) }
+ -5.5, 142mA,
+ -4.0, 140mA,
+ -3.0, 135mA,
+ -2.0, 120mA,
+ -0.6, 50mA,
+ 0.0, 0,
+ 0.5, -40mA
X1 A DPWR 74AC_CLAMP
G_OL DGND_OL DGND
+ TABLE { V(DGND_OL,DGND) }
+ -0.5, -70mA,
+ 0, 0,
+ 1.0, 120mA,
+ 1.6, 150mA,

4. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
+ 2.0, 160mA,
+ 3.0, 170mA,
+ 5.5, 172mA,
X2 DGND A 74AC_CLAMP
N1 A DGND_OL DPWR_OH DIN74AC244 DGTLNET=D IO_AC_DTOA
C1 A DGND {CAPACITANCE+0.01pF}
R1 A DGND 1G
.ends
.subckt 74AC_Clamp A C
G_Clamp A C TABLE { V(A,C) }
+ 0.0, 8uA
+ 0.5, 1mA
+ 5.5, 1A
.ends
.model DO74AC244 doutput (
+ s0name="X" s0vlo=0.299 s0vhi=0.715
+ s1name="0" s1vlo=-0.5 s1vhi=0.299
+ s2name="R" s2vlo=0.299 s2vhi=0.55
+ s3name="R" s3vlo=0.45 s3vhi=0.715
+ s4name="X" s4vlo=0.299 s4vhi=0.715
+ s5name="1" s5vlo=0.715 s5vhi=7
+ s6name="F" s6vlo=0.45 s6vhi=0.715
+ s7name="F" s7vlo=0.299 s7vhi=0.55
+ )
.model DO74AC244_NX doutput (
+ s0name="0" s0vlo=-1.5 s0vhi=1.5
+ s2name="1" s2vlo=1.5 s2vhi=7.0
+ )
.model DIN74AC244 dinput (
+ s0name="0" s0tsw=0.7ns s0rlo=1.0 s0rhi=2000K
+ s1name="1" s1tsw=0.7ns s1rlo=100K s1rhi=1
+ s2name="X" s2tsw=0.7ns s2rlo=104 s2rhi=100
+ s3name="R" s3tsw=0.7ns s3rlo=104 s3rhi=100
+ s4name="F" s4tsw=0.7ns s4rlo=104 s4rhi=100
+ s5name="Z" s5tsw=0.7ns s5rlo=200K s5rhi=200K
+ )
.MODEL IO_AC_DTOA UIO()
*$

5. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
G An Yn (Measurement) Yn (Simulation)
%Error
L L L L 0
TimeTime
0s 0.5us 1.0us
U1:1GBAR
U1:2GBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
U1:1Y1
U1:1Y2
U1:1Y3
U1:1Y4
U1:2Y1
U1:2Y2
U1:2Y3
U1:2Y4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LO
V1
5
R1
1MEG
LO
0
LO
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND 2A1
1Y4
2A2
1Y3
2A3
1Y2
2A4
1Y1
2G
VCC
_ U1
74AC244
LO
LO
LO
LO
LO LO
LO

6. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
G An Yn (Measurement) Yn (Simulation)
%Error
L H H H 0
TimeTime
0s 0.5us 1.0us
U1:1GBAR
U1:2GBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
U1:1Y1
U1:1Y2
U1:1Y3
U1:1Y4
U1:2Y1
U1:2Y2
U1:2Y3
U1:2Y4
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
HI
V1
5
HI
0
LO
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND 2A1
1Y4
2A2
1Y3
2A3
1Y2
2A4
1Y1
2G
VCC
_
_
U1
74AC244
LO
HI
R1
1MEG
HI
HI
HI
HI
HI

7. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
G An Yn (Measurement) Yn (Simulation)
%Error
H X Z Z 0
TimeTime
0s 0.5us 1.0us
U1:1GBAR
U1:2GBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
U1:1Y1
U1:1Y2
U1:1Y3
U1:1Y4
U1:2Y1
U1:2Y2
U1:2Y3
U1:2Y4
1
1
0
0
0
0
0
0
0
0
Z
Z
Z
Z
Z
Z
Z
Z
R1
1MEG
CLK
DSTM1
OFFTIME = .2uS
ONTIME = .2uS
HI
HI
V1
5
X
X
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND 2A1
1Y4
2A2
1Y3
2A3
1Y2
2A4
1Y1
2G
VCC
_
_
U1
74AC244
0

8. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level and Low Level Input Voltage
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 5.5V Measurement Simulation %Error
VIH (V) 3.85 3.9328 2.151
VIL (V) 1.65 1.6447 -0.321
Time
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(OUT) V(V1:+)
0V
2.0V
4.0V
6.0V
(529.904u,1.6447)
(571.505u,3.9328)
Output
Input
LO
0
OUT
LO
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND 2A1
1Y4
2A2
1Y3
2A3
1Y2
2A4
1Y1
2G
VCC
_
_
U1
74AC244
R3
1MEG
V1
TD = 0.5m
TF = 0.1m
PW = 1m
PER = 2m
V1 = 0
TR = 0.1m
V2 = 5.5
V2
5.5

9. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level and Low Level Output Voltage
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 4.5V Measurement Simulation %Error
VOH (V) 4.5 4.4988 -0.027
VOL (V) 0 0 0
Time
0s 5ms 10ms
V(V1:+)
0V
2.5V
5.0V
V(Y1)
0V
2.5V
5.0V
SEL>>
Output
Input
V1
TD = 0.5m
TF = 3n
PW = 1m
PER = 2m
V1 = 0.8
TR = 3n
V2 = 2.2
I2
-50u
LO
V2
3
LO
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND 2A1
1Y4
2A2
1Y3
2A3
1Y2
2A4
1Y1
2G
VCC
_
_
U1
74AC244
VOH
0

10. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Propagation Delay Time
Circuit simulation result
Evaluation circuit
Comparison table CL = 50 pF, RL = 500 Ω
VCC = 5 V, tr = tf = 3 ns Measurement Simulation %Error
tPLH (ns) 5.2 5.3997 3.840
tPHL (ns) 5.2 5.3093 2.102
Time
0s 0.5us 1.0us
1 V(TPLH) 2 V(V1:+)
0V
2.5V
5.0V
1
0V
2.5V
5.0V
2
>>
Output
Input
R1
500
LO
C1
50p
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND 2A1
1Y4
2A2
1Y3
2A3
1Y2
2A4
1Y1
2G
VCC
_
_
U1
74AC244
V1TD = 0.2u
TF = 3.8n
PW = 0.5u
PER = 1u
V1 = 0
TR = 3.8n
V2 = 5
0
V2
5
LO tplh

11. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time, high impedance (off) to high output (tPZH)
Output disable time, high to high impedance (off) output (tPHZ)
Circuit simulation result
Evaluation circuit
Comparison table CL = 50 pF, RL = 500 Ω
VCC = 5 V, tr = tf = 3 ns Measurement Simulation %Error
tPZH (ns) 5.9 5.9927 1.571
tPHZ (ns) 5.5 5.5810 1.473
Time
0s 0.5us 1.0us
1 V(TPZH_TPHZ) 2 V(V1:+)
0V
2.5V
5.0V
1
0V
2.5V
5.0V
2
>>
Output
Input
0
V1TD = 0.2u
TF = 3.8n
PW = 0.5u
PER = 1u
V1 = 0
TR = 3.8n
V2 = 5
V2
5
HI
C1
50p
R2
500
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND 2A1
1Y4
2A2
1Y3
2A3
1Y2
2A4
1Y1
2G
VCC
_
_
U1
74AC244
tpzh_tphz
R1
500
HI

12. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time, high impedance (off) to low output (tPZL)
Output disable time, low to high impedance (off) output (tPLZ)
Circuit simulation result
Evaluation circuit
Comparison table CL = 50 pF, RL = 500 Ω
VCC = 5 V, tr = tf = 3 ns Measurement Simulation %Error
tPZL (ns) 5.9 5.9775 1.314
tPLZ (ns) 5.5 5.5675 1.227
Time
0s 0.5us 1.0us
1 V(TPZL_TPLZ) 2 V(V1:+)
0V
2.5V
5.0V
1
0V
2.5V
5.0V
2
>>
Output
Input
tpzl_tplz R2
500
R1
500
V1TD = 0.2u
TF = 3.8n
PW = 0.5u
PER = 1u
V1 = 0
TR = 3.8n
V2 = 5
V3
5
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND 2A1
1Y4
2A2
1Y3
2A3
1Y2
2A4
1Y1
2G
VCC
_
_
U1
74AC244
C1
50p
0
HILO
V2
10