1. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Device Modeling Report
Bee Technologies Inc.
COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT
PART NUMBER : TC74VHC244F
MANUFACTURER : TOSHIBA

2. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
2A4
2Y4
GND
2Y2
_
_
1Y1
1A1
1Y3
2Y1 1Y4
1A3 2A3
2A2
2Y3
VCC1G
2G
2A1
1A4
1A2
1Y2
U1
74VHC244
SPICE MODEL
*$
*PART NUMBER : TC74VHC244F
*MANUFACTURER : TOSHIBA
*OCTAL BUS BUFFER, NON-INVERTED, 3-STATE OUTPUTS
*All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
.subckt 74vhc244 1GBAR 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 DGND
+ 2A1 1Y4 2A2 1Y3 2A3 1Y2 2A4 1Y1 2GBAR DPWR
+ params: MNTYMXDLY=0 IO_LEVEL=0
UAB inva(2) DPWR DGND
+ 1GBAR 2GBAR G1 G2
+ D0_GATE IO_VHC244 IO_LEVEL={IO_LEVEL}
U1 buf3a(4) DPWR DGND
+ 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4
+ D_VHC244 IO_VHC244 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
U2 buf3a(4) DPWR DGND
+ 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4
+ D_VHC244 IO_VHC244 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
.ends
.model D_VHC244 utgate (
+ tplhmn=1ns tplhty=3.6ns tplhmx=6.5ns
+ tphlmn=1ns tphlty=4.2ns tphlmx=6.5ns
+ tpzhmn=1ns tpzhty=4.6ns tpzhmx=8ns
+ tpzlmn=1ns tpzlty=5.2ns tpzlmx=9.3ns
+ tphzmn=1ns tphzty=3.6ns tphzmx=8ns
+ tplzmn=1ns tplzty=3.8ns tplzmx=8.9ns
+ )
.model IO_VHC244 uio (
+ drvh=35.3 drvl=46.9
+ inld=4pF
+ AtoD1="AtoD_VHC244"AtoD2="AtoD_VHC244_NX"

3. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
+ AtoD3="AtoD_VHC244"AtoD4="AtoD_VHC244_NX"
+ DtoA1="DtoA_VHC244"DtoA2="DtoA_VHC244"
+ DtoA3="DtoA_VHC244"DtoA4="DtoA_VHC244"
+ tswhl1=529ps tswlh1=695ps
+ tswhl2=513ps tswlh2=718ps
+ tswhl3=529ps tswlh3=695ps
+ tswhl4=513ps tswlh4=718ps
+ DIGPOWER="DIGIFPWR" tpwrt=2.9ns
+ )
.subckt AtoD_VHC244 A D DPWR DGND
+ params: CAPACITANCE=0
X1 DGND A VHC_CLAMP
X2 A DPWR VHC_CLAMP
ENORM NORM DGND VALUE={V(A,DGND)/(V(DPWR,DGND)+1U)}
O0 NORM DGND DO74VHC244 DGTLNET=D IO_VHC244
C1 A DGND {CAPACITANCE+0.1pF}
D0 DGND a D74SCLMP
D1 1 2 D74
D2 2 DGND D74
D3 3 1 D74
D4 3 A D74
D5 1 a D74S
R1 DPWR 3 370k
.ends
.subckt AtoD_VHC244_NX A D DPWR DGND
+ params: CAPACITANCE=0
ENORM NORM DGND VALUE={V(A,DGND)/(V(DPWR,DGND)+1U)}
O0 NORM DGND DO74VHC244_NX DGTLNET=D IO_VHC244
C1 A DGND {CAPACITANCE+0.1pF}
D0 DGND a D74SCLMP
D1 1 2 D74
D2 2 DGND D74
D3 3 1 D74
D4 3 A D74
D5 1 a D74S
R1 DPWR 3 3700k
.ends
.subckt DtoA_VHC244 D A DPWR DGND
+ params: DRVL=0 DRVH=0 CAPACITANCE=0
N1 A DGND DPWR DIN74VHC244 DGTLNET=D IO_VHC244
C1 A DGND {CAPACITANCE+0.1pF}
.ends
.model DO74VHC244 doutput (
+ s0name="X" s0vlo=0.299 s0vhi=0.725
+ s1name="0" s1vlo=-0.2 s1vhi=0.299

4. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
+ s2name="R" s2vlo=0.299 s2vhi=0.55
+ s3name="R" s3vlo=0.45 s3vhi=0.725
+ s4name="X" s4vlo=0.299 s4vhi=0.725
+ s5name="1" s5vlo=0.725 s5vhi=1.3
+ s6name="F" s6vlo=0.45 s6vhi=0.725
+ s7name="F" s7vlo=0.299 s7vhi=0.55
+ )
.model D74SCLMP d (
+ is=1e-11 vj=.7 rs=2 cjo=2pf
+ )
.model D74 d (
+ is=1e-16 rs=25 cjo=2pf
+ )
.model D74S d (
+ is=1e-12 vj=.7 rs=25 cjo=2pf
+ )
.model DO74VHC244_NX doutput (
+ s0name="0" s0vlo=-1.5 s0vhi=1.40
+ s2name="1" s2vlo=1.4 s2vhi=7.0
+ )
.model DIN74VHC244 dinput (
+ s0name="0" s0tsw=1.0ns s0rlo=40 s0rhi=1000K
+ s1name="1" s1tsw=1.0ns s1rlo=1000K s1rhi=41.4
+ s2name="X" s2tsw=1.0ns s2rlo=49.4 s2rhi=127
+ s3name="R" s3tsw=1.0ns s3rlo=49.4 s3rhi=127
+ s4name="F" s4tsw=1.0ns s4rlo=49.4 s4rhi=127
+ s5name="Z" s5tsw=1.0ns s5rlo=200K s5rhi=200K
+ )
.subckt VHC_Clamp A C
G_Clamp A C TABLE { V(A,C) }
+ 0.0, 4uA
+ 0.5, 1mA
+ 5.5, 1A
.ends
*$

5. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
G An Yn (Measurement) Yn (Simulation)
%Error
L L L L 0
TimeTime
0s 0.5us 1.0us
U1:1GBAR
U1:2GBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
U1:1Y1
U1:1Y2
U1:1Y3
U1:1Y4
U1:2Y1
U1:2Y2
U1:2Y3
U1:2Y4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2A4
2Y4
GND
2Y2
_
_
1Y1
1A1
1Y3
2Y1 1Y4
1A3 2A3
2A2
2Y3
VCC1G
2G
2A1
1A4
1A2
1Y2
U1
74VHC244
V1
5
R1
1MEG
LO
LO
0
LO
LO
LO
LO
LO
LO
LO
LO

6. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
G An Yn (Measurement) Yn (Simulation)
%Error
L H H H 0
TimeTime
0s 0.5us 1.0us
U1:1GBAR
U1:2GBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
U1:1Y1
U1:1Y2
U1:1Y3
U1:1Y4
U1:2Y1
U1:2Y2
U1:2Y3
U1:2Y4
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
HI
HI
HI
HI
HI
2A4
2Y4
GND
2Y2
_
_
1Y1
1A1
1Y3
2Y1 1Y4
1A3 2A3
2A2
2Y3
VCC1G
2G
2A1
1A4
1A2
1Y2
U1
74VHC244
HI
LO
0
R1
1MEG
HI
HI LO
V1
5

7. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
G An Yn (Measurement) Yn (Simulation)
%Error
H X Z Z 0
TimeTime
0s 0.5us 1.0us
U1:1GBAR
U1:2GBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
U1:1Y1
U1:1Y2
U1:1Y3
U1:1Y4
U1:2Y1
U1:2Y2
U1:2Y3
U1:2Y4
1
1
0
0
0
0
0
0
0
0
Z
Z
Z
Z
Z
Z
Z
Z
R1
1MEG
CLK
DSTM1
OFFTIME = .2uS
ONTIME = .2uS
X
V1
5
2A4
2Y4
GND
2Y2
_
_
1Y1
1A1
1Y3
2Y1 1Y4
1A3 2A3
2A2
2Y3
VCC1G
2G
2A1
1A4
1A2
1Y2
U1
74VHC244
X
0
HI
HI

8. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level and Low Level Input Voltage
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 5 V Measurement Simulation %Error
Min VIH = (VCC*0.7) V 3.5 3.6252 3.577
Min VIL = (VCC*0.3) V 1.5 1.4951 -0.327
Time
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(OUT) V(V1:+)
0V
2.0V
4.0V
6.0V
(529.901u,1.4951)
(572.504u,3.6252)
Output
Input
V1
TD = 0.5m
TF = 0.1m
PW = 1m
PER = 2m
V1 = 0
TR = 0.1m
V2 = 5
LO
LO
V2
5
0
2A4
2Y4
GND
2Y2
_
_
1Y1
1A1
1Y3
2Y1 1Y4
1A3 2A3
2A2
2Y3
VCC1G
2G
2A1
1A4
1A2
1Y2
U1
74VHC244
OUT
R3
1MEG

9. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level and Low Level Output Voltage
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 4.5V Measurement Simulation %Error
VOH (V) 4.5 4.4978 -0.049
VOL (V) 0 0 0
Time
0s 5ms 10ms
V(U1:1A1)
0V
2.5V
5.0V
V(OUT)
0V
2.5V
5.0V
SEL>>
Output
Input
LO
0
R1
0.09MEG
V2
4.5
2A4
2Y4
GND
2Y2
_
_
1Y1
1A1
1Y3
2Y1 1Y4
1A3 2A3
2A2
2Y3
VCC1G
2G
2A1
1A4
1A2
1Y2
U1
74VHC244
V1TD = 0.5m
TF = 3n
PW = 1m
PER = 2m
V1 = 0
TR = 3n
V2 = 4.5
LO

10. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Propagation Delay Time
Circuit simulation result
Evaluation circuit
Comparison table CL = 50 pF
VCC = 5 Vtr = tf =3 ns Measurement Simulation %Error
tPLH (ns) 5.4 5.4513 0.950
tPHL (ns) 5.4 5.4677 1.254
Time
0s 0.5us 1.0us
1 V(TPLH_TPHL) 2 V(V1:+)
0V
2.5V
5.0V
1
0V
2.5V
5.0V
2
>>
Output
Input
V1TD = 0.2u
TF = 3.8n
PW = 0.5u
PER = 1u
V1 = 0
TR = 3.8n
V2 = 5
tplh_tphlLO
LO
V2
5
C1
50p
2A4
2Y4
GND
2Y2
_
_
1Y1
1A1
1Y3
2Y1 1Y4
1A3 2A3
2A2
2Y3
VCC1G
2G
2A1
1A4
1A2
1Y2
U1
74VHC244
0

11. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time, high impedance (off) to high output (tPZH)
Output disable time, high to high impedance (off) output (tPHZ)
Circuit simulation result
Evaluation circuit
Comparison table CL = 50 pF, RL = 1 kΩ
VCC = 5 Vtr = tf =3 ns Measurement Simulation %Error
tPZH (ns) 6.2 6.2419 0.676
tPHZ (ns) 6.7 6.7540 0.806
Time
0s 0.5us 1.0us
1 V(TPZH_TPHZ) 2 V(V1:+)
0V
2.5V
5.0V
1
0V
2.5V
5.0V
2
>>
Output
Input
HI
0
HI
R1
1K
tpzh_tphz
2A4
2Y4
GND
2Y2
_
_
1Y1
1A1
1Y3
2Y1 1Y4
1A3 2A3
2A2
2Y3
VCC1G
2G
2A1
1A4
1A2
1Y2
U1
74VHC244
V1TD = 0.2u
TF = 3.8n
PW = 0.5u
PER = 1u
V1 = 0
TR = 3.8n
V2 = 5
V2
5
R2
1K
C1
50p

12. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time, high impedance (off) to low output (tPZL)
Output disable time, low to high impedance (off) output (tPLZ)
Circuit simulation result
Evaluation circuit
Comparison table CL = 50 pF, RL = 1 kΩ
VCC = 5 Vtr = tf =3 ns Measurement Simulation %Error
tPZL (ns) 6.2 6.2156 0.252
tPLZ (ns) 6.7 6.7531 0.793
Time
0s 0.5us 1.0us
1 V(TPZL_TPLZ) 2 V(V1:+)
0V
2.5V
5.0V
1
0V
2.5V
5.0V
2
>>
Output
Input
R1
1K
V1TD = 0.2u
TF = 3.8n
PW = 0.5u
PER = 1u
V1 = 0
TR = 3.8n
V2 = 5
R2
1K2A4
2Y4
GND
2Y2
_
_
1Y1
1A1
1Y3
2Y1 1Y4
1A3 2A3
2A2
2Y3
VCC1G
2G
2A1
1A4
1A2
1Y2
U1
74VHC244
0
HI
C1
50p
LO
V3
5
tpzl_tplz
V2
10