1. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Device Modeling Report
Bee Technologies Inc.
COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT
PART NUMBER : TC74VHCT244AFT
MANUFACTURER : TOSHIBA

2. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
2Y3
1A4
1A2
1Y4
_
2G
2Y2
2A3
2A4
1G
2A2
1Y3
GND 2A1
1A1
_
1Y2
VCC
2Y4
1A3
2Y1
1Y1
U1
VHCT244A
SPICE MODEL
*$
*PART NUMBER : TC74VHCT244AFT
*MANUFACTURER : TOSHIBA
*OCTAL BUS BUFFER, NON-INVERTED, 3-STATE OUTPUTS
*All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
.subckt vhct244a 1GBAR 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 DGND
+ 2A1 1Y4 2A2 1Y3 2A3 1Y2 2A4 1Y1 2GBAR DPWR
+ params: MNTYMXDLY=0 IO_LEVEL=0
UAB inva(2) DPWR DGND
+ 1GBAR 2GBAR OE1 OE2
+ D0_GATE IO_VHCT244 IO_LEVEL={IO_LEVEL}
U1 buf3a(4) DPWR DGND
+ 1A1 1A2 1A3 1A4 OE1 1Y1 1Y2 1Y3 1Y4
+ D_VHCT244 IO_VHCT244 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
U2 buf3a(4) DPWR DGND
+ 2A1 2A2 2A3 2A4 OE2 2Y1 2Y2 2Y3 2Y4
+ D_VHCT244 IO_VHCT244 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
.ends
.model D_VHCT244 utgate (
+ tplhmn=1ns tplhty=4.3ns tplhmx=8.4ns
+ tphlmn=1ns tphlty=4.0ns tphlmx=8.4ns
+ tpzhmn=1ns tpzhty=6.4ns tpzhmx=11.4ns
+ tpzlmn=1ns tpzlty=6.4ns tpzlmx=11.4ns
+ tphzmn=1ns tphzty=5.9ns tphzmx=11.4ns
+ tplzmn=1ns tplzty=5.9ns tplzmx=11.4ns
+ )
.model IO_VHCT244 uio (
+ drvh=24.5 drvl=18.7
+ inld=5pF
+ AtoD1="AtoD_VHCT244" AtoD2="AtoD_VHCT244_NX"

3. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
+ AtoD3="AtoD_VHCT244" AtoD4="AtoD_VHCT2444_NX"
+ DtoA1="DtoA_VHCT244" DtoA2="DtoA_VHCT244"
+ DtoA3="DtoA_VHCT244" DtoA4="DtoA_VHCT244"
+ tswhl1=477ps tswlh1=470ps
+ tswhl2=477ps tswlh2=470ps
+ tswhl3=477ps tswlh3=470ps
+ tswhl4=477ps tswlh4=470ps
+ DIGPOWER="DIGIFPWR"
+ )
.subckt AtoD_VHCT244 A D DPWR DGND
+ params: CAPACITANCE=0
X1 DGND A VHCT_CLAMP
X2 A DPWR VHCT_CLAMP
C1 A DGND {CAPACITANCE+0.01pF}
O0 A DGND DO74VHCT244 DGTLNET=D IO_VHCT244
.ends
.subckt AtoD_VHCT244_NX A D DPWR DGND
+ params: CAPACITANCE=0
X1 DGND A VHCT_CLAMP
X2 A DPWR VHCT_CLAMP
C1 A DGND {CAPACITANCE+0.01pF}
O0 A DGND DO74VHCT244_NX DGTLNET=D IO_VHCT244
.ends
.subckt DtoA_VHCT244 D A DPWR DGND
+ params: DRVL=0 DRVH=0 CAPACITANCE=0
G_OH DPWR DPWR_OH
+ TABLE { V(DPWR_OH,DPWR) }
+ -5.5, 71mA,
+ -4.0, 70mA,
+ -3.0, 67.5mA,
+ -2.0, 60mA,
+ -0.6, 25mA,
+ 0.0, 0,
+ 0.5, -20mA
X1 A DPWR VHCT_CLAMP
G_OL DGND_OL DGND
+ TABLE { V(DGND_OL,DGND) }
+ -0.5, -35mA,
+ 0, 0,
+ 1.0, 60mA,
+ 1.6, 75mA,
+ 2.0, 80mA,
+ 3.0, 85mA,
+ 5.5, 86mA,
X2 DGND A VHCT_CLAMP

4. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
N1 A DGND_OL DPWR_OH DIN74VHCT244 DGTLNET=D IO_AC_DTOA
C1 A DGND {CAPACITANCE+0.01pF}
R1 A DGND 1G
.ends
.subckt VHCT_Clamp A C
G_Clamp A C TABLE { V(A,C) }
+ 0.0, 4uA
+ 0.5, 1mA
+ 5.5, 1A
.ends
.model DO74VHCT244 doutput (
+ s0name="X" s0vlo=0.799 s0vhi=2.0
+ s1name="0" s1vlo=-1.5 s1vhi=0.799
+ s2name="R" s2vlo=0.799 s2vhi=1.55
+ s3name="R" s3vlo=1.45 s3vhi=2.0
+ s4name="X" s4vlo=0.799 s4vhi=2.0
+ s5name="1" s5vlo=2.0 s5vhi=7.0
+ s6name="F" s6vlo=1.45 s6vhi=2.0
+ s7name="F" s7vlo=0.799 s7vhi=1.55
+ )
.model DO74VHCT244_NX doutput (
+ s0name="0" s0vlo=-1.5 s0vhi=2
+ s2name="1" s2vlo=2 s2vhi=7.0
+ )
.model DIN74VHCT244 dinput (
+ s0name="0" s0tsw=0.7ns s0rlo=28 s0rhi=1000K
+ s1name="1" s1tsw=0.7ns s1rlo=100k s1rhi=1
+ s2name="X" s2tsw=0.7ns s2rlo=104 s2rhi=100
+ s3name="R" s3tsw=0.7ns s3rlo=104 s3rhi=100
+ s4name="F" s4tsw=0.7ns s4rlo=104 s4rhi=100
+ s5name="Z" s5tsw=0.7ns s5rlo=200K s5rhi=200K
+ )
.MODEL IO_AC_DTOA UIO()
*$

5. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
G An Yn (Measurement) Yn (Simulation)
%Error
L L L L 0
TimeTime
0s 0.5us 1.0us
U1:1GBAR
U1:2GBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
U1:1Y1
U1:1Y2
U1:1Y3
U1:1Y4
U1:2Y1
U1:2Y2
U1:2Y3
U1:2Y4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LO
R1
1MEG
LO
LO
2Y3
1A4
1A2
1Y4
_
2G
2Y2
2A3
2A4
1G
2A2
1Y3
GND 2A1
1A1
_
1Y2
VCC
2Y4
1A3
2Y1
1Y1
U1
VHCT244A
0
V1
5
LO
LO
LO
LO
LO
LO
LO

6. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
G An Yn (Measurement) Yn (Simulation)
%Error
L H H H 0
TimeTime
0s 0.5us 1.0us
U1:1GBAR
U1:2GBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
U1:1Y1
U1:1Y2
U1:1Y3
U1:1Y4
U1:2Y1
U1:2Y2
U1:2Y3
U1:2Y4
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
V1
5
HI HI
HI
HI
HI
HI
0
R1
1MEG
LO
HI
LO
2Y3
1A4
1A2
1Y4
_
2G
2Y2
2A3
2A4
1G
2A2
1Y3
GND 2A1
1A1
_
1Y2
VCC
2Y4
1A3
2Y1
1Y1
U1
VHCT244A
HI

7. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
G An Yn (Measurement) Yn (Simulation)
%Error
H X Z Z 0
TimeTime
0s 0.5us 1.0us
U1:1GBAR
U1:2GBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
U1:1Y1
U1:1Y2
U1:1Y3
U1:1Y4
U1:2Y1
U1:2Y2
U1:2Y3
U1:2Y4
1
1
0
0
0
0
0
0
0
0
Z
Z
Z
Z
Z
Z
Z
Z
V1
5
HI
X
2Y3
1A4
1A2
1Y4
_
2G
2Y2
2A3
2A4
1G
2A2
1Y3
GND 2A1
1A1
_
1Y2
VCC
2Y4
1A3
2Y1
1Y1
U1
VHCT244A
0
CLK
DSTM1
OFFTIME = .2uS
ONTIME = .2uS
R1
1MEG
HI
X

8. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level and Low Level Input Voltage
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 5V Measurement Simulation %Error
VIH (V) 2 2 0
VIL (V) 0.8 0.799195 -0.101
Time
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(OUT) V(V1:+)
0V
2.5V
5.0V
(515.984u,799.195m)
(540.005u,2.0003)
Output
Input
OUT
V1
TD = 0.5m
TF = 0.1m
PW = 1m
PER = 2m
V1 = 0
TR = 0.1m
V2 = 5
V2
5
2Y3
1A4
1A2
1Y4
_
2G
2Y2
2A3
2A4
1G
2A2
1Y3
GND 2A1
1A1
_
1Y2
VCC
2Y4
1A3
2Y1
1Y1
U1
VHCT244A
LO
R1
1G
LO
0

9. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level and Low Level Output Voltage
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 4.5V Measurement Simulation %Error
VOH (V) 4.5 4.4976 -0.053
VOL (V) 0 0 0
Time
0s 5ms 10ms
V(U1:1A1)
0V
2.5V
5.0V
V(OUT)
0V
2.5V
5.0V
SEL>>
Output
Input
LO
LO
2Y3
1A4
1A2
1Y4
_
2G
2Y2
2A3
2A4
1G
2A2
1Y3
GND 2A1
1A1
_
1Y2
VCC
2Y4
1A3
2Y1
1Y1
U1
VHCT244A
0
V1
TD = 0.5m
TF = 3n
PW = 1m
PER = 2m
V1 = 0
TR = 3n
V2 = 4.5
V2
4.5
R1
0.09MEG
OUT

10. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Propagation Delay Time
Circuit simulation result
Evaluation circuit
Comparison table CL = 50 pF
tr = tf =3 ns Measurement Simulation %Error
tPLH (ns) 5.9 5.9782 1.325
tPHL (ns) 5.9 5.9327 0.554
Time
0s 0.5us 1.0us
1 V(TPLH_TPHL) 2 V(V1:+)
0V
2.5V
5.0V
1
0V
1.5V
3.0V
2
>>
Output
Input
0
LO tplh_tphl
V2
5
V1TD = 0.2u
TF = 3.8n
PW = 0.5u
PER = 1u
V1 = 0
TR = 3.8n
V2 = 3
2Y3
1A4
1A2
1Y4
_
2G
2Y2
2A3
2A4
1G
2A2
1Y3
GND 2A1
1A1
_
1Y2
VCC
2Y4
1A3
2Y1
1Y1
U1
VHCT244A
C1
50p
LO

11. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time, high impedance (off) to high output (tPZH)
Output disable time, high to high impedance (off) output (tPHZ)
Circuit simulation result
Evaluation circuit
Comparison table CL = 50 pF, RL = 1 KΩ
tr = tf =3 ns Measurement Simulation %Error
tPZH (ns) 8.2 8.2441 0.538
tPHZ (ns) 8.8 8.9224 1.391
Time
0s 0.5us 1.0us
1 V(TPHZ_TPZH) 2 V(V1:+)
0V
2.5V
5.0V
1
0V
1.0V
2.0V
3.0V
2
>>
Output
Input
HI
tphz_tpzhHI
R2
1k
C1
50p
R1
1k
2Y3
1A4
1A2
1Y4
_
2G
2Y2
2A3
2A4
1G
2A2
1Y3
GND 2A1
1A1
_
1Y2
VCC
2Y4
1A3
2Y1
1Y1
U1
VHCT244A
V1TD = 0.2u
TF = 3.8n
PW = 0.5u
PER = 1u
V1 = 0
TR = 3.8n
V2 = 3 V2
5
0

12. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time, high impedance (off) to low output (tPZL)
Output disable time, low to high impedance (off) output (tPLZ)
Circuit simulation result
Evaluation circuit
Comparison table CL = 50 pF, RL = 1 KΩ
tr = tf =3 ns Measurement Simulation %Error
tPZL (ns) 8.2 8.2238 0.290
tPLZ (ns) 8.8 8.8277 0.315
Time
0s 0.5us 1.0us
1 V(TPZL_TPLZ) 2 V(V1:+)
0V
2.5V
5.0V
1
0V
1.5V
3.0V
2
>>
Output
Input
V3
5
V1TD = 0.2u
TF = 3n
PW = 0.5u
PER = 1u
V1 = 0
TR = 3n
V2 = 3
2Y3
1A4
1A2
1Y4
_
2G
2Y2
2A3
2A4
1G
2A2
1Y3
GND 2A1
1A1
_
1Y2
VCC
2Y4
1A3
2Y1
1Y1
U1
VHCT244A
V2
10
HI
tpzl_tplz
R2
1k
R1
1k
0
C1
50p
LO