TPLH Simulation
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This document describes the timing parameters of a BU7230G buffer gate. The propagation delay from a low input to a high output is TPLH. The input is driven by a 1.4V pulse with a 10 microsecond pulse width that repeats every 1000 microseconds. The output is loaded with a 15 picofarad capacitor and drives a 10 kiloohm resistor load referenced to ground.
![Propagation delay [ L to H ] - TPLH
VSS
VDD
IN-
+-
OUT
IN+
U1
BU7230G
V1
TD = 1u
TF = 0.5n
PW = 10u
PER = 1000u
V1 = 1.4V
TR = 0.5n
V2 = 1.6V
0
0
Vref 1
1.5
V
0
VDD
3V
0
VRL
3V
0
RL
10k
OUT
CL
15p](https://image.slidesharecdn.com/tplh22nov2013-150428053623-conversion-gate02/85/TPLH-Simulation-1-320.jpg)
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TPLH Simulation
- 1. Propagation delay [ L to H ] - TPLH VSS VDD IN- +- OUT IN+ U1 BU7230G V1 TD = 1u TF = 0.5n PW = 10u PER = 1000u V1 = 1.4V TR = 0.5n V2 = 1.6V 0 0 Vref 1 1.5 V 0 VDD 3V 0 VRL 3V 0 RL 10k OUT CL 15p