The following resources come from the 2009/10 BEng in Digital Systems and Computer Engineering (course number 2ELE0065) from the University of Hertfordshire. All the mini projects are designed as level two modules of the undergraduate programmes. The objectives of this module are to demonstrate, within an embedded development environment: Processor – to – processor communication Multiple processors to perform one computation task using parallel processing This project requires the establishment of a communication protocol between two 68000-based microcomputer systems. Using ‘C’, students will write software to control all aspects of complex data transfer system, demonstrating knowledge of handshaking, transmission protocols, transmission overhead, bandwidth, memory addressing. Students will then demonstrate and analyse parallel processing of a mathematical problem using two processors. This project requires two students working as a team.

4. Day 1 Communication between Two Processors

7. Asynchronous Communication BH Dual Processor Computation Addr AS Data DTACK 1. AS signals valid address available on address bus – start of transfer 2. DTACK is asserted to signal that the data has been stored 4. ACK is negated to signal ready for next transfer 3. AS is negated to signal transfer complete Addr AS Data DTACK Master Slave

8. Asynchronous Communication with Only Two Handshaking Signals BH Dual Processor Computation Master Strobe Slave ACK I have data for you! Thanks, I’ve stored it! I might send some more Ok, I’m ready

12. Preparation – Resource map BH Dual Processor Computation Variable name Possible states Input or Output Allocated port pin

14. Modular Structure BH Dual Processor Computation This is only an example ! main function 1 function 2 function 3 function 4 function 5 function 6

17. Day 2 Dual Processor Computation

22. Asynchronous Communication with Only Two Handshaking Signals BH Dual Processor Computation Master Strobe Slave ACK I have data for you! Thanks, I’ve stored it! I might send some more Ok, I’m ready

23. Handshake Cycle Time BH Dual Processor Computation Strobe ack time Unit transfer time 1 st cycle 2 nd cycle (µ s)

26. If one processor does the calculation BH Dual Processor Computation x = a*b/e y = c+d z = x/y This is how long it would take a single processor to calculate z Processor 1 time

27. Two processors sharing the calculation BH Dual Processor Computation Processor 1 Processor 2 x = a*b/e y = c+d z = x/y time

28. Two processors sharing the calculation BH Dual Processor Computation Processor 1 x = a*b/e y = c+d z = x/y time to transfer data to processor 1 time Processor 2 tc

29. Two processors sharing the calculation BH Dual Processor Computation Processor 1 y = c+d z = x/y time Processor 2 tc x = a*b/e

30. Two processors sharing a calculation BH Dual Processor Computation time x = a*b/e y = c+d z = x/y Processor 1 x = a*b/e y = c+d z = x/y Processor 2 tc time saving over single processor

31. Two processors sharing a calculation BH Dual Processor Computation Processor 1 x = a*b/e y = c+d z = x/y time Processor 2 tc Processor 1 x = a*b/e y = c+d z = x/y Processor 2 tc time saving over single processor Single processor x = a*b/e y = c+d z = x/y

32. Time saving in first computation BH Dual Processor Computation Processor 1 tx y = c+d tz time Processor 2 tc Processor 1 tx y = c+d tz Processor 2 tc Single processor ty ty time saving over single processor tx ty tz

33. Repeated Computation – see improved time saving during 1 st repetition of calculation BH Dual Processor Computation tx tc tx tz tc tx tc ty tx tc tz tz tz ty ty ty End of 1 st calculation tx tz Single processor ty time saving over single processor P1 P2 P1 P2

36. BH Dual Processor Computation Repeated Computation – see improved time saving during 1 st repetition of calculation tx tc tx tz tc tx tc ty tx tc tz tz tz ty ty ty tx tz Single processor ty P1 P2 12 12 14 8 P1 P2

38. BH Dual Processor Computation For this project, your level of preparation will be assessed. We will look at your logbook and the materials you have chosen to bring with you

39. Preparation – Resource map BH Dual Processor Computation Variable name Possible states Input or Output Allocated port pin

43. Reflection Cycle BH Dual Processor Computation Reflection Observation Action

46. This resource was created by the University of Hertfordshire and released as an open educational resource through the Open Engineering Resources project of the HE Academy Engineering Subject Centre. The Open Engineering Resources project was funded by HEFCE and part of the JISC/HE Academy UKOER programme. © University of Hertfordshire 2009 This work is licensed under a Creative Commons Attribution 2.0 License . The name of the University of Hertfordshire, UH and the UH logo are the name and registered marks of the University of Hertfordshire. To the fullest extent permitted by law the University of Hertfordshire reserves all its rights in its name and marks which may not be used except with its written permission. The JISC logo is licensed under the terms of the Creative Commons Attribution-Non-Commercial-No Derivative Works 2.0 UK: England & Wales Licence. All reproductions must comply with the terms of that licence. The HEA logo is owned by the Higher Education Academy Limited may be freely distributed and copied for educational purposes only, provided that appropriate acknowledgement is given to the Higher Education Academy as the copyright holder and original publisher.