Mini Project- ROM Based Sine Wave Generator

Mini Project – ROM-Based Sine Wave Generator

Author: University of Hertfordshire
Date created:
Date revised: 2009

Abstract
The following resources come from the 2009/10 BEng in Digital Systems and Computer Engineering (course number
2ELE0065) from the University of Hertfordshire. All the mini projects are designed as level two modules of the
undergraduate programmes.

The objectives of this module are to demonstrate, within an embedded development environment:

• Processor – to – processor communication
• Multiple processors to perform one computation task using parallel processing

This project requires the establishment of a communication protocol between two 68000-based microcomputer systems.
Using ‘C’, students will write software to control all aspects of complex data transfer system, demonstrating knowledge
of handshaking, transmission protocols, transmission overhead, bandwidth, memory addressing. Students will then
demonstrate and analyse parallel processing of a mathematical problem using two processors. This project requires two
students working as a team.

Contents
Mini Project – ROM-Based Sine Wave Generator...............................................................................................1
Section 2. Project Day 1.......................................................................................................................................4
Section 3. Project Day 2.......................................................................................................................................5
Section 4. Preparation Session- Introduction to Altium Designer 6 ....................................................................8
Credits.................................................................................................................................................................19

In addition to the resources found below there are supporting documents which should be used in combination with this
resource. Please see:
Mini Projects - Introductory presentation.
Mini Projects - E-Log.
Mini Projects - Staff & Student Guide.
Mini Projects - Standard Grading Criteria.
Mini Projects - Reflection.

You will also need the ‘Mini Project- ROM-Based Sine Wave Generator’ presentation.

© University of Hertfordshire 2009 This work is licensed under a Creative Commons Attribution 2.0 License.

Mini Projetc ROM-Based Sine Wave Generator

Section 1. Project Specification
1. Learning Outcomes assessed (as taken from the DMD)
All Learning Outcomes specified in the Definitive Module Documentation are assessed as part of this miniproject, the
specific Learning Outcomes are:
Knowledge and Understanding
Successful students will typically:
• Identify and enhance knowledge gained from other studies in areas relevant to the project topic selected.

Skills and Attributes
Successful students will typically:
• Use relevant measurement instruments to analyse a defined electronic engineering problem relevant to digital
systems or embedded computer systems.
• Synthesise a solution to a defined electronic engineering problem relevant to digital systems or embedded
computer systems.
• Take, and analyse appropriately, test results from that solution.
• Carry out a simple critical evaluation of the results taken.

2. Project Title: ROM-Based Sine Wave Generator

3. Project Objectives: (technical, specific to this project)
Demonstrate within the Altium Designer environment:
• An understanding of the principles of digital waveform generators
• the use of a hardware description language to implement a digital circuit
• the use of a test pattern to simulate a digital circuit

4. Project Summary: (50 words max)
Each student will be required to design and implement a ROM-based sine wave generator using a hybrid VHDL and
schematic on Field Programmable Gate Array (FPGA). The design process will include the production of a test pattern to
simulate the design before hardware implementation.

5. Introductory Lecture (2hrs) Content:
i. VHDL Design Styles
ii. Basic principles of sequential circuit design using VHDL - Memories
iii. Writing VHDL Testbenches
iv. Development tools to be used

6. Preparation Session (3hrs):
i. Familiarisation with the Altium Designer environment
ii. Writing a VHDL code for a sequential circuit
iii. Writing a VHDL testbench for a sequential circuit

7. Day 1
Expected Outcomes for the day:
Students working individually must carry out a series of tasks to implement the sine wave generator. The tasks include
the implementation and simulation of the generator’s basic component which is the ROM using a suitable VHDL design
style. A briefing pack which contains instructions and sine wave samples will be provided at the start of the day.

Assessment criteria; successful implementation using VHDL of a ROM that contains sine wave samples and
justification of the VHDL design style used. Use of a test pattern to successfully simulate the designed ROM.

Key Tasks:
• Implementation of a ROM that contains sine wave samples using VHDL
• Writing a VHDL test bench to simulate the ROM

FB Version 1.0 Page 2 of 19


8. Day 2

Expected Outcomes for the day:
Students are expected to use the ROM designed in day 1 to implement the sine wave generator on FPGA using a
schematic document. The students are also expected to monitor and analyse the generator’s output using a Logic
Analyzer soft device.

Assessment criteria; successful implementation of a sine wave generator using schematic on FPGA and use of a
Logic Analyzer soft device to monitor and analyse the output.

Key Tasks:
• Creation of a sheet symbol from the VHDL file written in day 1 and use it in a new schematic document to
implement the sine wave generator
• Implementation of the generator on FPGA
• Use a Logic Analyzer soft device available from Altium Designer’s instruments library to monitor and analyse
the generator’s output

9. Facilitator guidance (key ideas to draw out from students):
Day 1: Suitable VHDL design style to design sequential circuits
Day 2: FPGA design flow and use of a Logic Analyzer soft device

10. Required Resources: Laboratory Facilities and Teaching Support.
Laboratory Resources: LD403
1. PC Workstations with Altium Designer 6 (AD6), DXP simulator and Xilinx ISE.
2. NanoBoard-NB1 FPGA board.

Teaching Resources:
1. Preparatory Session; LD403: structured workshop based on an AD6 sequential design.
2. Day 1: briefing pack containing instructions for the day.
3. Day 2: briefing pack containing instructions for the day.



Section 2. Project Day 1
Tasks for the day

1. Use VHDL to describe the ROM shown in Figure 1 that contains the following 128 samples of a sine
wave

"10000000" "11111111" "10000000" "00000000"
"10000110" "11111111" "01111001" "00000000"
"10001100" "11111111" "01110011" "00000000"
"10010010" "11111110" "01101101" "00000001"
"10011000" "11111101" "01100111" "00000010"
"10011111" "11111100" "01100000" "00000011"
"10100101" "11111010" "01011010" "00000101"
"10101011" "11111000" "01010100" "00000111"
"10110000" "11110110" "01001111" "00001001"
"10110110" "11110011" "01001001" "00001100"
"10111100" "11110000" "01000011" "00001111"
"11000001" "11101101" "00111110" "00010010"
"11000111" "11101010" "00111000" "00010101"
"11001100" "11100110" "00110011" "00011001"
"11010001" "11100010" "00101110" "00011101"
"11010101" "11011110" "00101010" "00100001"
"11011010" "11011010" "00100101" "00100101"
"11011110" "11010101" "00100001" "00101010"
"11100010" "11010001" "00011101" "00101110"
"11100110" "11001100" "00011001" "00110011"
"11101010" "11000111" "00010101" "00111000"
"11101101" "11000001" "00010010" "00111110"
"11110000" "10111100" "00001111" "01000011"
"11110011" "10110110" "00001100" "01001001"
"11110110" "10110000" "00001001" "01001111"
"11111000" "10101011" "00000111" "01010100"
"11111010" "10100101" "00000101" "01011010"
"11111100" "10011111" "00000011" "01100000"
"11111101" "10011000" "00000010" "01100111"
"11111110" "10010010" "00000001" "01101101"
"11111111" "10001100" "00000000" "01110011"
"11111111" "10000110" "00000000" "01111001"

ADDR 8x128 ROM DATA

RE

CE

CLK

Figure 1. 8x128 ROM

2. Produce a test pattern and simulate your design using the DXP simulator.

3. Use VHDL to describe a counter that can be used to generate the ROM’s addresses

4. Produce a test pattern and simulate your counter using the DXP simulator.



Section 3. Project Day 2

Tasks for the day

1. Finish all tasks from Day 1.

2. Using the same FPGA project from Day 1, create sheet symbols from the ROM and counter VHDL
files and place them in a new schematic document.

3. Place the following components (listed below in Table 1) on the schematic sheet.

Table 1. Components to be used in schematic
Component name Available from FPGA integrated library
LAX_1K8 (Logic Analyzer) FPGA Instruments.IntLib
CLOCK_BOARD FPGA NB1 Port-Plugin.IntLib
CDIV4 FPGA Generic.IntLib
NEXUS_JTAG_CONNECTOR FPGA NB1 Port-Plugin.IntLib
NEXUS_JTAG_PORT FPGA Generic.IntLib

4. Wire the NEXUS_JTAG_CONNECTOR and NEXUS_JTAG_CONNECTOR as shown in Figure 1.

P8 JTAG_NEXUS_TDI TDI JTAG
JTAG
P11 JTAG_NEXUS_TDO TDO JTAG
P9 JTAG_NEXUS_TCK TCK JTAG
P10 JTAG_NEXUS_TMS TMS .
JTAG
.
.
JTAG
VCC TRST

Figure 1.

5. Connect the ROM and the counter (Leave the clock and the memory data pins unconnected).

Verifying the design using a logic analyzer
The LAX_x family of devices provide a range of 8- or 16-channel Logic Analyzer instruments for use in an
FPGA design. They provide a simple method of analyzing the logical levels of signals. In this mini-project,
the Logic Analyzer device to be used is the LAX_1K8. This device has 1Kx8 storage memory built-in. All 8
input channels are to be used to monitor the corresponding outputs of the 8-bit ROM.
The capture clock signal, CLK_CAP, is derived from the external system clock (CLOCK_BOARD). A
divide-by-4 clock divider is to be used. This makes the CLK_CAP, the ROM’s clock and the counter’s clock
signals four times slower than the system clock. CLK_CAP must be slower than CLK, otherwise the Logic
Analyzer will not capture data at all [1].

In order to communicate with soft devices in a design you must enable the soft devices JTAG chain within the
design. This is done by placing a JTAG Port (NEXUS_JTAG_CONNECTOR) and corresponding Soft
Nexus-Chain Connector (NEXUS_JTAG_PORT) on the top schematic sheet of the design, as shown in
Figure 2.

6. Based on the above description, wire the Logic Analyzer (STATUS signal to be left unconnected).



7. Save the schematic and the project then compile it. Resolve any errors and re-compile the project to
check.

8. Demonstrate your schematic to the lab supervisor.

9. Go to the Devices view (View » Devices) and click on Program FPGA to run all the stages of
compilation, synthesis, building and programming the FPGA chip.

10. To access the controls for the Logic Analyzer, simply double-click on the icon for that device in the
Soft Device chain. The Instrument Rack-Soft Devices panel will appear with, with the chosen device
added to the rack.

Graphical Display of the Captured Data

Captured data can be displayed in both analogue and digital waveform format. Access to the respective
waveform views is made through the Analyzer's Instrument panel.

Digital Waveforms
Pressing the Show Waves button associated to Digital output, in the Data Views region of the Logic
Analyzer's Instrument panel , will load the captured data into a digital wave file
(*.LaxDig) and open the file as the active document view. The data captured for all input channels will be
graphically displayed in the Waveform Analysis window.

Analogue Waveforms
Pressing the Show Waves button associated to Analog output, in the Data Views region of the Logic
Analyzer's Instrument panel , will load the captured data into an analogue wave file
(*.LaxAn) and open the file as the active document view. The data captured for all input channels will be
graphically displayed in the Waveform Analysis window.

A correct VHDL implementation should give the following analogue waveform:



11. Demonstrate your analogue waveform to the lab supervisor.

References

[1] Core reference, “LAX_x Logic Analyzer”, CR0103, v1.2, December 2005.



Section 4. Preparation Session- Introduction to Altium Designer 6

The aim of this session is to introduce the student to the Altium Designer 6 software. An overview and
step-by-step instructions will be given to guide the student through creating an FPGA design. The
session outlines how to create an FPGA project and then compile, synthesise, build and download to
program the Xilinx Spartan IIE chip on the daughterboard of the Altium NanoBoard. The
implementation of a D flip-flop with synchronous RESET using schematic/VHDL will be used as an
example.

Intended Learning Outcomes

By the end of this lab session students should be able to:

1.Create an FPGA project
2.Create a hybrid VHDL/Schematic design
3.Write a VHDL Testbench
4.Simulate a VHDL design
5.Configure a design to an FPGA

1. Creating an FPGA Project

To create a new project:

1. Select File » New » Project » FPGA Project from the
menu

2. Rename the new project file (with a .PrjFPG extension)
by selecting File » Save Project As. Type the name
FPGA_DFF in the file name field and click on Save.

1.1 Adding a VHDL file to the project

1. Right-click on the FPGA project name and select Add New to Project » VHDL Document, type in
the following code and save the document under the name d_ff.VHD.



Figure 1. d_ff.VHD.

2. Check the syntax of the VHDL code by Selecting Project » Compile Document [VHDL_file_name].
Any syntax error messages will automatically appear in the Messages panel. You must manually
display the panel by clicking on the System tab at the bottom of the design window and selecting
Messages (or select View » Workspace Panels » System » Messages from the menus).

3. Resolve any errors and re-compile the file to check. Save the VHDL file and project file.

1.2 Simulation

In this section, you will create a VHDL test bench that defines the desired functionality for the VHDL
module. This test bench is then used in conjunction with DXP simulator to verify that the VHDL module
meets the behavioural requirements.

1. Click on Design » Create VHDL Testbench. A testbench Test_dff.VHDTST is created and opened.

2. In the testbench, insert the following statements:



3. Add an initial value to the signal CLK as follows:

4. Select the simulation tool and the testbench document by right clicking the project file name in the
Projects panel and selecting Simulation tab from within the Project Options dialog.

Figure 2. Project options.

5. Select the simulation tool DXP Simulator from the drop-down list for Tool.
1
6. Select the testbench document “Test_df.VHDTST” from the drop-down list for Testbench Document
and click the OK button.

7. Initiate a simulation session by selecting Simulator » Simulate from the menu.



8. When you first run a simulation from a testbench, the following window will be shown.

Figure 3. Project compile order

9. If the correct compile order is shown as in the above window, click the No button. The following
window will be shown.

Figure 4. Simulation signals

10. Click the Done button. The following window will be shown.



Figure 5. Simulation window

11. Run the simulation to a time by clicking the button Run Simulation To A Time . The following
window will be shown. Change the time to 100 ns and click the OK button.

Figure 6. Simulation time

12. The following window will be shown. Observe the simulation result. After the simulation, you can
change the zoom and the time cursor to check the signal values

Figure 7. Simulation result

13. Save the simulation result in a wave file by clicking on the Save button in the menu.

14. The simulation can be reset by clicking Simulation » Reset from the menu.



15. The simulation can be terminated by clicking Simulation » End.

16. Other simulation results can be obtained by changing the statements in the stimulus process of the
testbench.

2. Creating a Schematic source document

An FPGA project supports two types of source documents – schematic and HDL. You can mix both types of
documents in a project with the use of sheet symbols. However, for FPGA projects, a schematic must be used
for the top level document of your project. In this section, we will use the VHDL file of the D flip-flip to
create a schematic symbol then connect it to some components on the NanoBoard.

To create a single schematic document for the D flip-flop:

1. Select File » New » Schematic. A blank schematic sheet named Sheet1.SchDoc displays in the design
window.

2. Rename the new schematic file (with a .SchDoc extension) by selecting File » Save As. Type the
name D_flip_flop.SchDoc in the File Name field and click on Save.

2.1 Creating a sheet symbol from a VHDL file

1. Next we will create a sheet symbol from the d_ff VHDL file. With the D_flip_flop.SchDoc schematic
open, create a new sheet symbol by selecting Design » Create Sheet Symbol from Sheet or HDL.
Select d_ff.VHD from the Choose Document to Place dialog and click OK. The sheet symbol appears
floating on the cursor. Press TAB to display its Sheet Symbol properties dialog. Click on the
Parameters tab to check that the VHDLEntity parameter has been added. Make sure the Visible
option is selected and click OK. Click to place the sheet symbol on the D_flip_flop schematic.
U_dff
d_ff.Vhd
CLK Q
D
SRESET
VHDLENTITY: dff

Figure 8. Sheet symbol for the VHDL file

If the VHDL file contains multiple entities, the VHDLENTITY parameter specifies which entity you
want to instantiate.

2.2 Placing parts on the schematic



The components we will need for this schematic can be found in
the NanoBoard Port-Plug-in library (NanoBoard Port-
Plugin.IntLib). This library is installed and available from the
Libraries panel by default.
Now, let’s start designing the schematic for our D flip-flop.

1. Select FPGA NanoBoard Port-Plugin.IntLib from the drop-
down list in the Libraries panel.

2. Find the component LED in the Libraries panel. You can
browse the Libraries panel by either navigating through the
list or typing the name LED (or part of the name) in the
Masks edit box below the library name. Select the component
in the list and click the Place LED button or simply drag
the selected Component Name onto the schematic sheet.

3. You should notice that your cursor now has the component
attached to it. Move the cursor into the schematic workspace
if you don’t see it. Place the component by clicking on
the appropriate position on the schematic.

4. We also need to use CLK_BRD, TEST_BUTTON and DIPSWITCH from the same library. Repeat
the above steps to place these components as shown in Figure 9. Note that these components have a
visible parameter named ‘PinNumberDisplay’ that initially reads as ‘PXX’ for each pin. When the
design is synthesised later, these parameters will be updated to display the pin numbers that these nets
connect to on the target FPGA.

5. We also require some components located in the FPGA Generic.IntLib, also a default library available
from the Libraries panel. Place J8B_8S and J8S_8B from this library as shown in Figure 9 below.

Figure 9. D flip-flop schematic with parts placed

6. Finally, add designators to the design using Tools » Annotate Schematics Quietly or Tools » Force
Annotate All Schematics. Designators will be automatically added to all the components in this
schematic.

2.3 Adding Power Ports

Place one GND power ports for ground.
1. Select Place » Power Port or click on the GND icon in the Wiring toolbar.



2. Right-click, or press ESC, to exit placement mode.

2.4 Creating connections

We have placed all the components and ports, so now it is time to wire them all together. Our design will
need both wires and buses. Let’s place the wires first.

1. To place a wire, select Place » Wire and click on the point on the schematic where you want to start
placing (usually at a port or a component pin). Move the cursor to the next point you want your wire
segment to connect to and click again. Continue until you have made a connection to another port or
component pin. Continue wiring and right-click, or press ESC, to exit wire placement mode.

2. Wire up the schematic as shown in Figure 10.

Figure 10. The D flip-flop schematic wired up

2.5 Naming the connections

It is always a good idea to net label all your connections as it will make your design easier to understand
and makes tracking down problems and referencing easier. To net label your connections:

1. Select Place » Net Label. A dotted box will appear floating on the cursor.

2. To edit the net label before it is placed, press the TAB key to display the Net Label dialog. Type the
net name in the Net field, e.g. LEFT. Click OK.
3. Place the net label so that the bottom left of the net label (its ‘hotspot’) touches the wire you want to
label. The cursor will change to a red cross when the net label touches the wire.

4. Label the other nets. The diagram below gives an indication where the net labels should be placed.
They need not be named exactly as shown in Figure 11, as long as they are unique. Right-click or
press ESC to exit net label placement mode.



clock U_dff
PXX CLK_BRD
d_ff.Vhd
U1
Q_out I0 O[7..0]
U2 CLK Q
I[7..0] O0 D_in I1
D
O1 I2
SRESET
O2 I3
O3 VHDLENTITY: dff I4
O4 I5
O5 I6
O6 I7
O7 J8S_8B
J8B_8S
reset GND
PXX TEST_BUTTON

Figure 11. The D flip-flop schematic with net labels added

2.6 Using Buses

Altium Designer supports the complex use of buses for FPGA designs. Buses can be used to specify not
just a group of signals but how each signal in the bus is mapped to its endpoints. When using buses, it is
important to remember that you always need to net label any disjointed bus segment. It is also useful to
note that a connection from a bus to another object is always resolved from left to right and the bus size of
both objects in a connection must be the same.
To connect the LED port to J8S_8B and the DIPSWITCH to J8B_8S:

1. Place a bus by selecting Place » Bus and place the bus, using the same placement technique used
when placing a wire.
U1
I0 O[7..0]
LEDS[7..0]
I1
PXX,PXX,PXX,PXX,PXX,PXX,PXX,PXX
I2
I3
I4
I5
I6
I7
J8S_8B

GND

Figure 12. Connecting the DIP switch port to J8B_8S using a bus.

2. Save the schematic and save the project.

2.7 Checking the design

Before we proceed, let’s check that the schematic is going to plan by compiling the project and running
the electrical and graphical checks set in the Error Checking tab of the Options for FPGA Project dialog
(Project » Project Options).
2. Select Project » Compile FPGA Project [project_name]. Any Error or Fatal Error messages will
automatically appear in the Messages panel.

3. Double-click on any error message in the Messages panel to display more information about the error
in the Compile Errors dialog. The offending entity will be zoomed into and highlighted in the
schematic.

4. Resolve any errors and re-compile the project to check. Save the schematic and project file.



3. Configuring your design

Now we need to specify which FPGA chip we want to use in our design, e.g. the Xilinx Spartan IIE
XC2S300E-6PQ208C chip on the NanoBoard daughterboard. We will add a configuration and constraint files
to do this. The Constraint file will determine the pin numbering and the device name to be used by the FPGA
chip on the NanoBoard.

1. Select Project » Configuration Manager. The Configuration Manager for project dialog appears.
Click on the Add button in the Configurations section of the dialog and type a configuration name in
the New Configuration Name dialog, e.g. NB_SpartanIIE, and click OK. Configuration names should
relate to the target implementation for easy identification.

2. Add a Constraints file to your configuration by clicking on the Add button in the Constraints section
and select NB1_6_XC2S300E-6PQ208.Constraint in the Choose Constraint files to add to Project
dialog. Constraint files are found in the Altium Designer 6LibraryFPGA NB1 Constraint Files
Xilinx FPGA folder. Click Open.

3. Select the configuration checkbox back in the Configuration Manager dialog and click OK.

Figure 13. Configuration manager

4. A folder named Settings is added to the project and shows the constraint file used in the Constraints
Files folder.

5. Save the project file.

1.1 Using the Devices view to program the FPGA

The Devices view (View » Devices View) allows you to follow through the workflow (from left to right)
required to send your program to the FPGA. In this view, you can:

• Compile the project (and check for errors)
• Synthesize (create an EDIF netlist)
• Build (e.g. translate the EDIF files, map the design to the FPGA, Place and Route the FPGA, run a
Timing Analysis and then Make the Bit File that can then be used to program the FPGA)
• Program FPGA (download the bit file to the daughter board’s FPGA chip, e.g. the Xilinx Spartan IIE).



Figure 14. Programming the FPGA

When this workflow is completed, you will be able to run the program by flicking on and off the DIP switches
(SW1 and SW2) on the NanoBoard. To download your D flip-flop design to the FPGA:

1. Make sure your NanoBoard is properly connected and switched on. In the Devices view, click on the
Live button and check that the Connected indicator is green.

2. In the Devices view, click on Compile. The red indicator will turn green when a successful
compilation takes place. If any error messages display in the Messages panel, go back to your
schematics, correct any errors, save the files and recompile.

3. Click on Synthesize. If the synthesis is completed successfully, a folder called Generated
[config_name] is created which holds the generated EDIF, VHDL and synthesis log file.
During synthesis, the source documents are translated into intermediate VHDL files which are then
synthesised into EDIF, suitable for vendor Place & Route tools. Errors detected during synthesis are
based on errors in the intermediate files, so go back to the source files to fix any problems. Double-
click on an error in the Messages panel to see the fault in the source documents and intermediary
VHDL.

4. Click on Build. This will step through several processes to ultimately make the Bit file that can be
downloaded to the FPGA. You will see the buttons next to the various processes turn green as they are
successfully completed. The Build button will turn green when all necessary processes are completed
and the Results Summary dialog appears.

5. Click on Program FPGA to download the bit file to the daughterboard’s Spartan chip.

6. When the Program FPGA process is completed, you will be able to run the program by flicking on and
off the DIP switch SW1 and pressing the test button on the NanoBoard. The DIP switch and the test
button are wired as active low devices, i.e. when a switch is ON the signal produced is low.



Credits

This resource was created by the University of Hertfordshire and released as an open educational
resource through the Open Engineering Resources project of the HE Academy Engineering Subject
Centre. The Open Engineering Resources project was funded by HEFCE and part of the JISC/HE
Academy UKOER programme.

Where screenshots are taken from Altium Designer 6, and appear courtesy of Premier EDA
Solutions Ltd.

© University of Hertfordshire 2009

This work is licensed under a Creative Commons Attribution 2.0 License.

Microsoft product screen shots reprinted with permission from Microsoft Corporation. Microsoft and Visual C# are either registered trademarks or
trademarks of Microsoft Corporation in the United States and/or other countries.

The name of the University of Hertfordshire, UH and the UH logo are the name and registered marks of the University of Hertfordshire. To the fullest
extent permitted by law the University of Hertfordshire reserves all its rights in its name and marks which may not be used except with its written
permission.

The JISC logo is licensed under the terms of the Creative Commons Attribution-Non-Commercial-No Derivative Works 2.0 UK: England & Wales
Licence. All reproductions must comply with the terms of that licence.

The HEA logo is owned by the Higher Education Academy Limited may be freely distributed and copied for educational purposes only, provided that
appropriate acknowledgement is given to the Higher Education Academy as the copyright holder and original publisher.


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