Chapter 10.pptx

CHAPTER 10
Digital CMOS Logic Circuits
1
* Slide numbers are given to facilitate you to note points.

Introduction
• CMOS: Complementary Metal Oxide Semiconductor
• CMOS: Most popular technology for implementation of
digital systems (chip designing)
• Advantages: Small size, ease of fabrication and low
power dissipation of MOSFETs
• Integrated-Circuit Design: Most significant area (at least in
terms of production volume and societal impact) of
electronic circuits
2

10.1 DIGITAL CIRCUIT DESIGN: AN
OVERVIEW
3

10.1.1 Digital IC Technologies and Logic-
Circuit Families
• Members of each family are made with the same
technology, have a similar structure, and exhibit the same
basic features.
• Normally, a logic family is selected, as much system
packages as possible are made and then interconnected
which is relatively straight-forward.
• If different logic families for same system packages are
used, then suitable interface circuits are to be designed
4

10.1.1 Digital IC Technologies and Logic-
Circuit Families
• The selection of logic family is based on considerations
such as:
• Logic flexibility
• Speed of operation
• Availability of complex functions
• Noise immunity
• Operating-temperature range
• Power dissipation
• Cost
• Other factors too…
5

10.1.1 CMOS
• Most dominant
• Replaced NMOS (Reason: Much lower power dissipation)
• Replaced Bipolar
• Much less power dissipation (can pack more CMOS circuits on a
chip)
• High input impedance of MOS transistor allows designer to use
charge storage as means for temporary storage of information in
both logic and memory circuits.
• Feature size(i.e. minimum channel length) of MOS transistor has
decreased dramatically over the years (0.06 μm) allowing tight
circuit packing with high levels of integration
6

10.1.1 CMOS
• Complementary CMOS:
• SSI(1-10 logic gates) on PCB
• MSI (10-100 gates per chip) on PCB
• VLSI ((106)millions of gates per chip)
• Used in memory design
• Dynamic logic:
• Faster circuit operation while keeping the power dissipation very
low.
7

10.1.1 Bipolar
• TTL or T2L
• Most widely used logic-circuit family for many years
• Decline due to VLSI era
• Fought back with introduction of low-power and high-speed
versions (avoid slow turnoff process by preventing BJT from
saturating)
• (Not studied during course)
• ECL (fastest)
• Current-switch implementation of the inverter
• Basic element: BJT differential pair
• High speeds of operation possible (since saturation is avoided)
• Used in VLSI where designer is willing to accept high power
dissipation and increased silicon area
8

10.1.1 BiCMOS and GaAs
• BiCMOS combines
• high operating speeds possible with BJTs
• Low power dissipation and other excellent characteristics of CMOS
• BiCMOS can implement both analog and digital circuits like CMOS
• GaAS
• The high carrier mobility in GaAs results in very high speed of
operation
• Emerging technology
• Not yet achieved potential to go commercial
• (Not studied in the course)
9

10.1.2 Logic-Circuit Characterization
Noise Margins
10

Power Dissipation
• Motivation: Desire to pack increasing number of gates on
a chip (Space and Economic considerations)
• Modern digital systems use large number of gates and
memory cells.
• To keep total power requirement within reasonable limit,
power dissipation per gate and per memory cell should be
kept as low as possible.
• E.g. Battery-Operated Equipment: Cellular Phones and
Personal Digital Assistants (PDAs)
12

Power Dissipation
• Power Dissipation: Static & Dynamic
• Static: absence of switching (Path b/w supply and ground
when output is high or low)
• Dynamic: During the switching of gate
• Inverter operated from a power supply VDD, and driving a
load capacitance C, dissipates dynamic power PD,
𝑃𝐷 = 𝑓𝐶𝑉𝐷𝐷
2
where f is the frequency at which the inverter is being
switched.
13

Delay-Power Product
• Best combination: High-speed performance with Low
power dissipation (often in conflict: trade-off)
• Attempts to reduce power include reducing supply voltage
and/or supply current decreasing current-driving capability
of gate which results in longer times to charge and
discharge the load and parasitic capacitances increasing
propagation delay
• Figure of merit: delay-power product: DP=PDtP (Joules)
• PD: power dissipation of gate.
14

Silicon Area
• Objective in VLSI: Minimization of silicon area per logic
gate
• Three techniques for reduction of silicon area:
• Advances in processing technology resulting in of minimum device
size
• Advances in circuit-design techniques (Area of interest in book)
• Careful chip layout
15

Silicon Area
• Circuit-design technique: Simpler circuit requires smaller area
• Circuit designer has to decide on device sizes.
• Smaller device size advantages
• Smaller silicon area
• Reducing parasitic capacitances increasing speed
• Smaller device size dis-advantages
• Lower current-driving capability increasing delay
• Trade-off quantification to optimize the critical aspect of design for
the application at hand
16

Fan-In and Fan-Out
• Fan-In: Number of inputs of a gate
• 4-input NOR gate, Fan-In:4
• Fan-out: maximum number of similar gates that a gate
can drive while remaining within guaranteed specifications
• Example: Increasing fan-out of BJT inverter reduces VOH
and hence NMH. So, to keep NMH above a certain
minimum, fan-out has to be limited to a calculable
maximum value.
17

10.1.3 Styles for Digital System Design
• Conventional approach: Assemble the system using
standard IC packages of various levels of complexity
(uses TTL,SSI and MSI packages)
• Advent of VLSI: Not only provides powerful off-the-shelf
components e.g. Microprocessors and Memory chips,
also made possible alternative design styles.
• One style: produce one or more custom VLSI chips
(Economically justified if production volume is large:
greater than about 100,000 parts)
18

10.1.3 Styles for Digital System Design
• Intermediate Approach: Semicustom Design utilizing gate-
array chips
• ICs containing 100,000 or more unconnected logic gates:
interconnection achieved by a final metallization step at IC
fabrication facility according to pattern specified by user
• FPGA(field-programmable gate array): can be
programmed directly by the user, very convenient means
for the digital-system designer to implement complex logic
functions in VLSI form
19

10.1.4 Design Abstraction and Computer
Aids
• Digital-Systems design, whether on a single IC chip or
using off-the-shelf components, is made possible by use
of different levels of design abstraction and a variety of
computer aids.
• Design abstraction with off-the-shelf packages of logic
gates: Designer needs to consult data-sheets to find i/p-
o/p characteristics, fan-in and fan-out limitations and so
on. Also, designer needs to adhere to a set of rules
specified by the manufacturers datasheet.
• No need to consider circuit inside the gate package rather
treat like a functional block.
20

Aids
• Digital-IC designer follows a similar process as above
simplifying system design.
• Circuit blocks are designed, characterized and stored in a library as
standard cells.
• These cells can then be used to assemble a larger subsystem (e.g.
an adder or a multiplier), which in turn is characterized and stored
as a function block to design an even larger system (e.g. an entire
processor).
• Every level of design abstraction is helped by computer
aids to make process as automated as possible.
• Computer aids make it humanly possible to design a 100-
million-transistor digital IC.
21

Aids
• Unfortunately, analog IC design does not lend itself to the
same level of abstraction and automation.
• Each analog IC to a large extent has to be “handcrafted”.
Due to this, the complexity and density of analog ICs
remain much below what is possible in digital IC.
• Whatever approach or style is adopted in digital design,
some familiarity with the various digital-circuit
technologies and design techniques is essential.
• This course aims to provide such a background.
22

iD-vDS characteristics of n-channel MOS
25

iD-vDS characteristics of n-channel MOS
26

iD-vSD characteristics of p-channel MOS
27

Graphical construction to determine the
operating point (vI=VDD)
28

Graphical construction to determine the
operating point (vI=0V)
29

13.2.1(6th Ed.) CMOS Inverter Circuit
Operation
1. VOL=0V & VOH=VDD means signal swing is maximum
possible. Also this inverter can be designed to provide a
symmetrical voltage-transfer characteristic, resulting in wide
noise margins.
2. Static power dissipation is zero (neglecting leakage
currents) in both its states. The reason being no dc path
exists b/w power supply and ground in either state.
3. A low-resistance path exists b/w o/p terminal & ground
(during low-o/p state) or VDD(in high-o/p state).
• These low-resistance paths ensure that o/p voltage is 0 or VDD
independent of the exact values of the W/L ratios or other device
parameters
• Furthermore, the low o/p resistance makes the inverter less sensitive
to effects of noise and other disturbances.
30

13.2.1(6th Ed.) CMOS Inverter Circuit
Operation
4. The active pull-up and pull-down devices provide
inverter with high o/p driving capability in both
directions speeding up the operation considerably.
5. The input resistance of the inverter is infinite(because
IG=0).
• Thus the inverter can drive an arbitrarily large number of similar
inverters with no loss in signal level. But each additional inverter
increases load capacitance on driving inverter slowing the
operation down.
31

13.2.2(6th Ed.) The Voltage-Transfer
Characteristic (matched QN and QP)
32

13.2.3(6th Ed.) The Situation When QN
and QP Are Not Matched
• QN,QP matched when Vtn=|Vtp| and kn=kp by selecting
Wp/Wn using equation
𝑊𝑝
𝑊𝑛
=
μ𝑛
μ𝑝
. In matched case,
symmetric VTC and 𝑉𝑀 =
𝑉𝐷𝐷
2
and NMH=NML.
• Symmetry in VTC is achieved by Wp=4Wn, resulting in a
large silicon area resulting in increased device
capacitance and propagation delay of inverter.
• Therefore, it is useful to inquire into the effect of not
matching QN and QP by deriving expression for VM.
33

• At VM, both QN and QP in saturation, equating the currents
and using vI=vo=VM, we get:
1
2
𝑘𝑛
′
𝑊
𝐿 𝑛
𝑉𝑀 − 𝑉𝑡𝑛
2
=
1
2
𝑘𝑝
′
𝑊
𝐿 𝑝
𝑉𝐷𝐷 − 𝑉𝑀 − |𝑉𝑡𝑝|
2
which gives us 𝑉𝑀 =
𝑟 𝑉𝐷𝐷− 𝑉𝑡𝑝 +𝑉𝑡𝑛
𝑟+1
where 𝑟 =
𝑘𝑝
𝑘𝑛
=
𝜇𝑝𝑊𝑝
𝜇𝑛𝑊𝑛
with Lp=Ln assumed
which is usually the case with L equal to minimum available
for the given process technology.
34

• Note that, for matched case r=1 and with Vtn=|Vtp|=Vt,
VM=VDD/2, even in the derived equation.
• With graph, we notice 2 points,
1. VM increases with r. Thus if kp>kn VM goes toward VDD and if
kp<kn VM shifts toward 0.
2. VM is not a strong function of r. For
the case shown, lowering r by a
factor of 2(from 1 to 0.5, reduces
VM by only 0.13 V.
• Thus if one is willing to tolerate a
small reduction in NML, silicon
area can be substantially saved.
35
L=0.18μm

13.3 (6th Ed.) Dynamic operation of the
CMOS Inverter
• Speed of operation of a digital system(e.g. a computer) is
determined by the propagation delay of logic gates used
to construct the system.
• Qualification of a technology is done on the basis of the
propagation delay of its inverter.
• To determine the propagation delay of a CMOS inverter,
we need to analyze its switching operation.
• We shall do this in two steps: 1) Finding the total C value
of the inverter. 2) Using the C value found to calculate
propagation delays, tp, tPLH and tPHL.
37

13.3.1 (6th Ed.) Determining the
Propagation Delay
38
t=0- t=0 t=0+ t=∞
QN: triode
QP: cut-off

Propagation Delay
39
QN: saturation
QN: triode

Propagation Delay: Observations
1. tPHL and tPLH can be equalized by selecting the (W/L) ratios to
equalize kn and kp, i.e., by matching QN and QP.
2. Since 𝑡𝑝 ∝ 𝐶. To reduce C, use minimum possible channel
length and also minimize wiring and other parasitic
capacitances. Careful layout of the chip can also result in
significant reduction in such capacitances.
3. Using a process technology with larger transconductance
parameter k′ can result in shorter propagation delays. Keep
in mind, however, that for such processes COX is increased,
and thus the value of C increases at the same time.
40

Propagation Delay
4. Also 𝑡𝑝 ∝
1
𝑊
𝐿
. However, increasing the size of the devices
increases the value of C, and thus the expected reduction in
tP might not materialize. Reducing tP by increasing W/L,
however, is an effective strategy when C is dominated by
components not directly related to the size of the driving
device (such as wiring or fan-out devices).
5. 𝑡𝑃 ∝
1
𝑉𝐷𝐷
. However, VDD is determined by the process
technology and thus is often not under the control of the
designer. Furthermore, modern process technologies in
which device sizes are reduced require lower VDD (see Table
7.A.1). A motivating factor for lowering VDD is the need to
keep the dynamic power dissipation at acceptable levels,
especially in very-high-density chips.
41

13.3.1(6th Ed.) Alternative Approach
42

13.3.2(6th Ed.): Determining the
Equivalent Load Capacitance (At vo)
44

13.3.2 (6th Ed.): Determining the
Equivalent Load Capacitance
1. Cgd1 and Cgd2 can be replaced as 2Cgd1 and 2Cgd2
between output node and ground utilizing Miller effect.
2. Each of Cdb1 and Cdb2 has a terminal at a constant
voltage. Thus for purpose of our analysis here, can be
replaced with equal capacitance between output and
ground. Equivalent large-signal values found(Hodges)
45

13.3.2 (6th Ed.): Determining the
Equivalent Load Capacitance
3. For input capacitances of Q3 & Q4 i.e. Cg3 & Cg4, each
one is equal to WLCox+Cgsov+Cgdov.
Thus Cg3+Cg4=(WL)3Cox+(WL)4Cox+Cgsov3+Cgdov3+Cgsov4+Cgdov4
4. Wiring Capacitance Cw adds to total value of C.
Thus C=2Cgd1+2Cgd2+Cdb1+Cdb2+Cg3+Cg4+Cw.
Ex 3.16(6th Ed.) Solve yourself.
46

13.3.3(6th Ed.): Inverter Sizing
• In this section we address the question of selecting appropriate
(W/L) ratios for the two transistors QN and QP in an inverter.
The reasoning can be summarized as follows.
1. To minimize area, the length of all channels is usually made
equal to the minimum length permitted by the given
technology.
2. In a given inverter, if our interest is strictly to minimize area,
(W/L)n is usually selected in the range 1 to 1.5. The selection
of (W/L)p relative to (W/L)n has influence on the noise
margins and tPLH. Both are optimized by matching QP and QN.
47

13.3.3(6th Ed): Inverter Sizing
2. (contd.) This, however, is usually wasteful of area and
equally important can increase the effective capacitance C,
so that although tPLH is made equal to tPHL, the value of both
can be higher than in the case without matching(Pb 13.40).
Thus, selecting (W/L)p=(W/L)n is a possibility, and
(W/L)p=2(W/L)n is a frequently used compromise.
3. Having settled on an appropriate ratio, we still have to select
(W/L)n to reduce tp allowing higher speeds of operation. Any
increase in (W/L)n and proportionally in (W/L)p will of course
increase area, and hence the inverter contribution to the
value of the equivalent capacitance C. To be more precise
we express C as the sum of an intrinsic component Cint
contributed by QN and QP of the inverter, and an extrinsic
component Cext resulting from the wiring and the input
capacitance of the driven gates,
C=Cint+Cext
48

13.3.4(6th Ed.): Dynamic Power
Dissipation
• The negligible static power dissipation of CMOS has been
a significant factor in its dominance as the technology of
choice in implementing high-density VLSI circuits.
• However, as the number of gates per chip steadily
increases, the dynamic power dissipation has become a
serious issue.
• The dynamic power dissipated in the CMOS inverter is
given by:
𝑃𝑑𝑦𝑛 = 𝑓𝐶𝑉𝐷𝐷
2
where f is the frequency at which the gate is switched.
49

Dissipation
• Minimizing C is an effective means for reducing dynamic-power
dissipation.
• More effective strategy is the use of a lower power-supply
voltage.
• As mentioned, CMOS process technologies now utilize VDD
values of 1 V or less.
• These newer chips, however, pack much more circuitry on the
chip (as many as 2.3 billion transistors) and operate at higher
frequencies (microprocessor clock frequencies above 3 GHz are
now available).
• The dynamic power dissipation of such high-density chips can be
over 100 W.
50

Dissipation
• In addition to the dynamic power dissipation, there is
another component of power dissipation that results from
the current that flows through QN and QP during every
switching event.
• Matched transistors,
Ipeak at VM=VDD/2 and
QN & QP in saturation.
𝐼𝑝𝑒𝑎𝑘 =
1
2
𝑘𝑛
′
𝑊
𝐿 𝑛
𝑉𝐷𝐷
2
− 𝑉𝑡𝑛
2
• In general, this component is
usually much smaller than Pdyn.
51

10.3.7: Summary of the Synthesis Method
1. The PDN can be most directly synthesized by expressing
𝑌 as a function of the uncomplemented variables. If
complemented variables appear in this expression,
additional inverters will be required to generate them.
2. The PUN can be most directly synthesized by expressing
Y as a function of the complemented variables. If
uncomplemented variables appear in this expression,
additional inverters will be required to generate them.
3. The PDN can be obtained from the PUN (and vice versa)
using the duality property.
52

Example 10.2
• Provide transistor W/L ratios for the logic circuit given in
example. Assume that for the basic inverter n = 1.5 and
p = 5 and that the channel length is 0.25 μm.
53

10.3.9: Effects of Fan-In and Fan-Out on
Propagation Delay
• Each additional input to a CMOS gate requires two
additional transistors, one NMOS and one PMOS.
• The additional transistors in CMOS not only increases the
chip area but also increases the total effective
capacitance per gate and in turn increases the
propagation delay.
• The size-scaling method described earlier compensates
for some (but not all) of the increase in tP. Specifically, by
increasing device size, we are able to preserve the
current-driving capability.
54

Propagation Delay
• However, the capacitance C increases because of both the
increased number of inputs and the increase in device size.
• Thus tP will still increase with fan-in, a fact that imposes a
practical limit on the fan-in of, say, the NAND gate to about 4. If
a higher number of inputs is required, then “clever” logic design
should be adopted to realize the given Boolean function with
gates of no more than four inputs.
• This would usually mean an increase in the number of
cascaded stages and thus an increase in delay. However, such
an increase in delay can be less than the increase due to the
large fan-in.
55

Propagation Delay
• An increase in a gate’s fan-out adds directly to its load
capacitance and, thus, increases its propagation delay.
• Thus although CMOS has many advantages, it does
suffer from increased circuit complexity when the fan-in
and fan-out are increased, and from the corresponding
effects of this complexity on both chip area and
propagation delay.
• In the following two sections, we shall study some
simplified forms of CMOS logic that attempt to reduce this
complexity, although at the expense of forgoing some of
the advantages of basic CMOS.
56

10.4: Pseudo-NMOS Logic Circuits
• Standard CMOS logic excels in almost every performance
category: It is easy to design, has the maximum possible
voltage swing, is robust from a noise-immunity standpoint,
dissipates no static power, and can be designed to
provide equal high-to-low and low-to-high propagation
delays.
• Its main disadvantage is the requirement of two
transistors for each additional gate input, which for gates
with high fan-in can make the chip area large and
increase the total capacitance and, correspondingly, the
propagation delay and the dynamic power dissipation.
57

• For this reason designers of digital integrated circuits
have been searching for forms of CMOS logic circuits that
can be used to supplement standard CMOS.
• These forms are not intended to replace complementary
CMOS but rather to be used in special applications for
special purposes.
• Two such CMOS logic styles examined in this course are
Pseudo-NMOS Logic and Pass Transistor Logic.
58

59

60
Vt
vo= vI- Vt
Vt
QN:c QN:s QN:t
QP :s
QP :t
QP :t
QP :t
QN:t

10.4.4: Dynamic Operation
• Analysis of the inverter transient response to determine
tPLH with the inverter loaded by a capacitance C is
identical to that of the complementary CMOS inverter.
• The capacitance will be charged by the current iDP; we
can determine an estimate for tPLH by using the average
value of iDP over the range vo = 0 to vo = VDD ⁄ 2. The result
is:
𝑡𝑃𝐿𝐻 =
1.7𝐶
𝑘𝑝𝑉𝐷𝐷
61

• The case for the capacitor discharge is somewhat
different because the current iDP has to be subtracted from
iDN to determine the discharge current. The result is
𝑡𝑃𝐻𝐿 ≅
1.7𝐶
𝑘𝑛 1−
0.46
𝑟
𝑉𝐷𝐷
• Which for larger value of r, reduces to
𝑡𝑃𝐻𝐿 =
1.7𝐶
𝑘𝑛𝑉𝐷𝐷
62

• Although these are similar formulas to those for the
standard CMOS inverter, the pseudo-NMOS inverter has
a special problem: Since kp is r times smaller than kn, tPLH
will be approximately r times larger than tPHL.
• Thus the circuit exhibits an asymmetrical delay
performance.
• Recall, however, that for gates with large fan-in, pseudo-
NMOS requires fewer transistors and thus C can be
smaller than in the corresponding standard CMOS gate.
63

10.4.5: Design
• The design involves selecting the ratio r and the W/L for
one of the transistors. The value of for the other device
can then be obtained using r. The design parameters of
interest are VOL, NML, NMH, Istat, PD, tPLH, and tPHL.
1. The ratio r determines all the breakpoints of the VTC;
the larger the value of r, the lower VOL is and the wider
the noise margins are. However, a larger r increases the
asymmetry in the dynamic response and, for a given
(W/L)p , makes the silicon area larger. Thus, selecting a
value for r represents a compromise between noise
margins on the one hand and silicon area and tP on the
other. Usually, r is selected in the range 4 to 10.
64

10.4.5: Design
2. Once r has been determined, a value for (W/L)p or
(W/L)n can be selected and the other determined. Here,
one would select a small (W/L)n to keep the gate area
small and thus obtain a small value for C. Similarly, a
small (W/L)p keeps Istat and PD low. On the other hand,
one would want to select larger W/L ratios to obtain low
tp and thus fast response. For usual (high-speed)
applications, (W/L)p is selected so that Istat is in the
range of 50 μA to 100 μA, which for VDD = 1.8 V results
in PD in the range of 90 μW to 180 μW.
65

10.4.6: Gate Circuits
• Except for the load device, the pseudo-NMOS gate circuit
is identical to the PDN of the complementary CMOS gate.
• Four-input, pseudo-NMOS NOR and NAND gates are
shown. (Draw on Board)
• Note that each requires five transistors compared to the
eight used in standard CMOS.
• In pseudo-NMOS, NOR gates are preferred over NAND
gates because the former do not utilize transistors in
series and thus can be designed with minimum-size
NMOS devices.
66

10.4.7: Concluding Remarks
• Pseudo-NMOS is particularly suited for applications in which
the output remains high most of the time.
• In such applications, the static power dissipation can be
reasonably low (since the gate dissipates static power only in
the low-output state).
• Further, the output transitions that matter would presumably be
high-to-low ones, where the propagation delay can be made as
short as necessary.
• A particular application of this type can be found in the design
of address decoders for memory chips and in read-only
memories (ROM). [Chapter 11]
67

Example 10.3
• Consider a pseudo-NMOS inverter fabricated in a 0.25-μm
CMOS technology for which μnCox=115 μA/V2, μpCox=30μA/V2,
Vtn = −Vtp = 0.4 V, and VDD = 2.5 V. Let the W/L ratio of QN be
(0.375 μm ⁄ 0.25 μm) and r = 9. Find:
a) VOH, VOL, VIL, VIH, VM, NMH, and NML
b) (W/L)P
c) Istat and PD
d) tPLH, tPHL, and tP, assuming a total capacitance at the inverter
output of 7fF
68

10.5.2: Operation with NMOS Transistors
as Switches:
69

Example 10.4
• Consider the NMOS transistor switch in the circuits of Figs.
10.26 and 10.27 to be fabricated in a technology for which
μnCox = 50μA/V2 μpCox = 20 μA/V2,|Vt0|=1V, γ = 0.5 V1/2,
2φf = 0.6 V, and VDD = 5 V, where φf is a physical parameter.
Let the transistor be of the minimum size for this technology,
namely, 4 μm/2 μm, and assume that the total capacitance
between the output node and ground is C = 50 fF.
a) For the case with vI high (Fig. 10.26), find VOH.
b) If the output feeds a CMOS inverter whose
(W/L)p=2.5(W/L)n= 10μm/2μm, find the static current of the
inverter and its power dissipation when its input is at the
value found in (a). Also find the inverter output voltage.
70

Example 10.4
• Consider the NMOS transistor switch in the circuits of Figs.
10.26 and 10.27 to be fabricated in a technology for which
μnCox = 50μA/V2 μpCox = 20 μA/V2,|Vt0|=1V, γ = 0.5 V1/2,
2φf = 0.6 V, and VDD = 5 V, where φf is a physical parameter.
Let the transistor be of the minimum size for this technology,
namely, 4 μm/2 μm, and assume that the total capacitance
between the output node and ground is C = 50 fF.
c) Find tPLH.
d) For the case with vI going low (Fig. 10.27), find tPHL.
e) Find tp.
71

10.5.2 Contd.: Restoring the value of VOH
to VDD (Level Restorer circuit)
72

10.5.3: The Use of CMOS Transmission
Gate as Switches
• Great improvements in static and dynamic performance are
obtained when the switches are implemented with CMOS
transmission gates.
• The transmission gate utilizes a pair of complementary
transistors connected in parallel. It acts as an excellent switch,
providing bidirectional current flow, and it exhibits an “on”
resistance that remains almost constant for wide ranges of
input voltage.
• These characteristics make the transmission gate not only an
excellent switch in digital applications but also an excellent
analog switch in such applications as data converters and
switched-capacitor filters.
73

Gate as Switches
• Recall that an NMOS transistor transmits the 0-V level to
the output perfectly and thus produces a “good 0.” It has
difficulty, however, in passing the level VDD, with the result
that VOH=VDD-Vt (a “poor 1”).
• It can be shown that a PMOS transistor does exactly the
opposite; that is, it passes the VDD level perfectly and thus
produces a “good 1” but has trouble passing the 0-V level,
thus producing a “poor 0.”
• It is natural therefore to think that placing an NMOS and a
PMOS transistor in parallel would produce good results in
both the 0 and 1 cases.
74

Gate as Switches
• Another way to describe the performance of the two
transistor types is that the NMOS is good at pulling the
output down to 0 V, while the PMOS is good at pulling the
output up to VDD.
• Interestingly, these are also the roles they play in the
standard CMOS inverter.
75

Gate as Switches
76

10.5.4: Pass-Transistor Logic Circuit
Examples
• Figure shows a PTL realization of a two-to-one
multiplexer: Depending on the logic value of C, either A or
B is connected to the output Y.
• The circuit realizes the Boolean function 𝑌 = 𝐶𝐴 + 𝐶𝐵
77

Examples
• Our second example is an efficient realization of the
exclusive-OR (XOR) function.
• The circuit utilizes four transistors in the transmission
gates and another four for the two inverters needed to
generate the complements 𝐴 and 𝐵, for a total of eight
transistors.
• Note that 12 transistors are needed in the realization with
standard CMOS.
78

Examples
• The final PTL example is the circuit shown in Fig. It uses NMOS
switches with low or zero threshold.
• Observe that both the input variables and their complements are
employed and that the circuit generates both the Boolean function
and its complement.
• Thus this form of circuit is known as complementary pass-transistor
logic (CPL). The circuit consists of two identical networks of pass
transistors with the corresponding transistor gates controlled by the
same signal (B and 𝐵).
• The inputs to the PTL, however, are complemented: A and B for the
first network, and 𝐴 and 𝐵 for the second.
• The circuit shown realizes both the AND and NAND functions.
79

10.5.5: A Final Remark
• Although the use of zero-threshold devices solves the
problem of the loss of signal levels when NMOS switches
are used, the resulting circuits can be much more
sensitive to noise and other effects, such as leakage
currents resulting from subthreshold conduction.
80

10.6: DYNAMIC LOGIC CIRCUITS
• The logic circuits that we have studied thus far are of the
static type.
• In a static logic circuit, every node has, at all times, a low-
resistance path to VDD or ground. By the same token, the
voltage of each node is well defined at all times, and no
node is left floating.
• Static circuits do not need clocks (i.e., periodic timing
signals) for their operation, although clocks may be
present for other purposes.
81

• In contrast, the dynamic logic circuits we are about to
discuss rely on the storage of signal voltages on parasitic
capacitances at certain circuit nodes.
• Since charge will leak away with time, the circuits need to
be periodically refreshed; thus the presence of a clock
with a certain specified minimum frequency is essential.
• To place dynamic logic circuit techniques into perspective,
let’s take stock of the various styles we have studied for
logic circuits.
82

• Standard CMOS excels in nearly every performance
category: It is easy to design, has the maximum possible
logic swing, is robust from a noise-immunity standpoint,
dissipates no static power, and can be designed to
provide equal low-to-high and high-to-low propagation
delays.
• Its main disadvantage is the requirement of two
transistors for each additional gate input, which for high
fan-in gates can make the chip area large and increase
the total capacitance and, correspondingly, the
propagation delay and the dynamic power dissipation.
83

• Pseudo-NMOS reduces the number of required transistors at
the expense of static power dissipation.
• Pass-transistor logic can result in simple small-area circuits but
is limited to special applications and requires the use of CMOS
inverters to restore signal levels, especially when the switches
are simple NMOS transistors.
• The dynamic logic techniques studied in this section maintain
the low device count of pseudo- NMOS while reducing the
static power dissipation to zero.
• As will be seen, this is achieved at the expense of more
complex, and less robust, design.
84

10.6.2: Nonideal Effects (Noise Margins)
• Since, during the evaluation phase, the NMOS transistors
begin to conduct for vI = Vtn,
𝑉𝐼𝐿 ≈ 𝑉𝐼𝐻 ≈ 𝑉𝑡𝑛
and thus the noise margins will be
𝑁𝑀𝐿 = 𝑉𝐼𝐿 − 𝑉𝑂𝐿 = 𝑉𝑡𝑛 − 0 = 𝑉𝑡𝑛
𝑁𝑀𝐻 = 𝑉𝑂𝐻 − 𝑉𝐼𝐻 = 𝑉𝐷𝐷 − 𝑉𝑡𝑛
• Thus the noise margins are far from equal, and NML is rather
low. Although NMH is high, other nonideal effects reduce its
value, as we shall shortly see.
• At this time, however, observe that the output node is a high-
impedance node and thus will be susceptible to noise pickup
and other disturbances.
87

10.6.2: Nonideal Effects (Output Voltage
Decay Due to Leakage Effects)
• In the absence of a path to ground through the PDN, the
output voltage will ideally remain high at VDD.
• This, however, is based on the assumption that the
charge on CL will remain intact.
• In practice, there will be leakage current that will cause CL
to slowly discharge and vY to decay.
88

10.6.2: Nonideal Effects (Output Voltage
Decay Due to Leakage Effects)
• The principal source of leakage is the reverse current of the
reverse-biased junction between the drain diffusion of
transistors connected to the output node and the substrate.
• Such currents can be in the range of 10-12 A to 10-15 A, and they
increase rapidly with temperature (approximately doubling for
every rise in temperature).
• Thus the circuit can malfunction if the clock is operating at a
very low frequency and the output node is not “refreshed”
periodically.
• This exact same point will be encountered when we study
dynamic memory cells in Chapter 11.
89

10.6.2: Nonideal Effects (Charge Sharing)
90

10.6.2: Nonideal Effects (Cascading)
91
=VDD =VDD
After precharge
VDD=
Correct result of Y1 and Y2?

10.6.2: Nonideal Effects (Charge Sharing)
92
=VDD =VDD
During Evaluation
VDD=
Vtn
0

10.6.3: Domino CMOS Logic (Cascaded)
94
0
0
VDD
0
VDD
0
0
0
VDD
PRECHARGE
EVALUATION
tPHL=0

95
1
1
VDD
0
VDD
1
1
0
VDD
EVALUATION
VDD/2
VDD/2
VDD/2
VDD
0
VDD
0
tPLH=finite

96
tPLH tPLH
VDD/2

10.6.4: Concluding Remarks
• Dynamic logic presents many challenges to the circuit
designer.
• Although it can provide considerable reduction in the chip-area
requirement, as well as high-speed operation, and zero (or
little) static-power dissipation, the circuits are prone to many
nonideal effects, some of which have been discussed here.
• It should also be remembered that dynamic power dissipation
is an important issue in dynamic logic.
• Another factor that should be considered is the “dead time”
during pre-charge when the output of the circuit is not yet
available.
97

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