1. Cache Memory
Exercises

2. Questions I
• Given:
– memory is little-endian and byte addressable;
memory size;
– number of cache blocks, size of cache block
– An instruction lw $t0, x or lbu $t0, x;
• Determine
– HIT or MISS?
– What value is in $t0?; and
– Show the cache after word is brought in if needed

3. Assume memory is little-endian and byte
Address Contents (Hex)
addressable; cache block = 1 word;
(binary)
Cache holds 4 blocks of data ( 4 words)
000000 aa bb cc dd
000100 00 11 00 33
001000 ff ee 01 23
V Tag data(hex)
001100 45 67 89 0a
0 10 11 11 00 01 00
010000 bc de f0 1a
1 00 00 01 01 33 01
010100 2a 3a 4a 5a
0 11 11 11 11 11 10
011000 6a 7a 8a 9a
1 00 45 67 89 0a 11
011100 1b 2b 3b 4b
100000 b2 b3 b4 b5
100100 c1 c2 c3 c4
101000 d1 d2 d3 d4
101100 e1 e2 e3 e4
110000 f1 f2 f3 f4
lbu $t0, x # x = 001101
110100 a1 a2 a3 a4
111000 2c 3c 4c 5c Question 1: cache HIT or
111100 2d 3d 4d 5d MISS? What is in $t0?
Draw the cache after
data is brought in

4. Assume memory is little-endian and byte
Address Contents (Hex)
addressable; cache block = 1 word;
(binary
) Cache holds 4 blocks of data ( 4 words)
000000 aa bb cc dd
000100 00 11 00 33
001000 ff ee 01 23 V Tag data(hex)
0 10 11 11 00 01 00
001100 45 67 89 0a
0 00 00 01 01 11 01
010000 bc de f0 1a
0 00 Ffee 01 23 10
010100 2a 3a 4a 5a
0 00 00 00 00 00 11
011000 6a 7a 8a 9a
011100 1b 2b 3b 4b
100000 b2 b3 b4 b5
100100 c1 c2 c3 c4
101000 d1 d2 d3 d4
101100 e1 e2 e3 e4
110000 f1 f2 f3 f4
lbu $t0, x # x = 001010
110100 a1 a2 a3 a4 Question 2: cache HIT or
111000 2c 3c 4c 5c MISS? What is in $t0?
111100 2d 3d 4d 5d
Draw the cache after
data is brought in

5. Assume memory is little-endian and byte
Address Contents (Hex)
addressable; cache block = 1 word;
(binary)
Cache holds 4 blocks of data ( 4 words)
000000 aa bb cc dd
000100 00 11 00 33
001000 ff ee 01 23
V Tag data(hex)
001100 45 67 89 0a
0 10 11 11 00 01 00
010000 bc de f0 1a
1 00 00 11 00 33 01
010100 2a 3a 4a 5a
0 11 11 11 11 11 10
011000 6a 7a 8a 9a
1 00 00 00 00 00 11
011100 1b 2b 3b 4b
100000 b2 b3 b4 b5
100100 c1 c2 c3 c4
101000 d1 d2 d3 d4
101100 e1 e2 e3 e4
110000 f1 f2 f3 f4
lbu $t0, x # x = 000111
110100 a1 a2 a3 a4
111000 2c 3c 4c 5c Question 3: cache HIT or
111100 2d 3d 4d 5d MISS? What is in $t0?
Draw the cache after
data is brought in

6. Assume memory is little-endian and byte
Address Contents (Hex)
addressable; cache block = 1 word;
(binary)
Cache holds 4 blocks of data ( 4 words)
000000 11 11 00 01
000100 00 11 00 33
001000 ff ee 01 23
V Tag data(hex)
001100 45 67 89 0a
0 01 11 11 00 01 00
010000 bc de f0 1a
1 00 00 01 01 11 01
010100 2a 3a 4a 5a
0 11 11 11 11 11 10
011000 6a 7a 8a 9a
1 00 00 00 00 00 11
011100 1b 2b 3b 4b
100000 b2 b3 b4 b5
100100 c1 c2 c3 c4
101000 d1 d2 d3 d4
101100 e1 e2 e3 e4
110000 f1 f2 f3 f4 lbu $t0, x # x = 010010
110100 a1 a2 a3 a4
111000 2c 3c 4c 5c
Question 4: cache HIT or
111100 2d 3d 4d 5d
MISS? What is in $t0?
Draw the cache after
data is brought in

7. Assume memory is little-endian and byte
Address Contents (Hex)
addressable; cache block = 1 word;
(binary)
Cache holds 4 blocks of data ( 4 words)
000000 aa bb cc dd
000100 00 11 00 33
001000 ff ee 01 23
V Tag data(hex)
001100 45 67 89 0a
0 10 11 11 00 01 00
010000 bc de f0 1a
0 00 00 01 01 11 01
010100 2a 3a 4a 5a
0 11 11 11 11 11 10
011000 6a 7a 8a 9a
0 00 00 00 00 00 11
011100 1b 2b 3b 4b
100000 b2 b3 b4 b5
100100 c1 c2 c3 c4
101000 d1 d2 d3 d4
101100 e1 e2 e3 e4
110000 f1 f2 f3 f4
lbu $t0, x # x = 011011
110100 a1 a2 a3 a4
111000 2c 3c 4c 5c Question 5: cache HIT or
111100 2d 3d 4d 5d MISS? What is in $t0?
Draw the cache after
data is brought in

8. Cache Question II-1
• Suppose: 256 bytes of memory, cache
holds 4 blocks, each block is 1 word.
What is the cache size?
• Answer:
aaaaaaaa  t t t t i i o o
cache: valid tag data
Cache size: 1 4 32
(4+1+32)*4 bits

9. Cache Question II-2
• Suppose: 256 bytes of memory, cache
holds 8 blocks , each block is 1 word.
What is the cache size?
• Answer:
aaaaaaaa  t t t i i i o o
cache: valid tag data
Cache size: 1 3 32
(3+1+32)*8 bits

10. Question II-3
• What is the cache size (total number of bits) for
a cache that holds 64KB of data (block == 1
word; 2**32 bytes of memory)
• Answer:
• 64KB == 16K words;
– 16K = (2**4) *(2**10) = 2**14
– So 14 bits are needed for the cache index
• Tag size = 32 – 14 -2 = 16 bits
• Cache size = (1 + (32-14-2) + 32) * (2**14)
= 784 K bits
= 98 KB