2. Wafer is a thin slice of semiconductor
material,such as silicon crystal,used in
fabriction of ic &other microdevices.
It serves as the substrate for microelectronic
devices
Wafers are formed of highly pure
99.99999999999%
3. It is the process by which die are separated
from a wafer of semiconductor following the
processing of the wafer.
It involve scribing,breaking,mechanical
sawing or laser cutting.
Following the process individual silicon chips
are encapsulated in to chip carrierswhich are
then suitable for use in building electronic
devices such as computers
4. Wafers are typically mounted on dicing tape
which has sticky backing that hold wafer on a
thin sheet metal frame.
Once a wafer has been diced the pieces left
on dicing tape are reffered to as die,dice,or
dies.
Each will be packaged in a suitable package
or placed directly on a printed circuit board.
5. The size of die left on tape may range from
35mm to .1mm
A full cut laser dicer has the ability to cut and
separate in a variety of shapes .
Materials diced include glass, alumina,
silicon, gallium arsenide , silicon on sapphire,
ceramics, and delicate compound
semiconductors.
7. Demonstration of cutting features in to
1.5mm thick si wafers using laser
micromachining system equipped with a qcw
laser.
Cut features are round holes, with no
cracking or rough edges.
The same system can be used to downsize
larger silicon wafers for use in smaller format
processing tools.
8. Wafer process is a procedure composed of
many repeated sequential process to produce
complete electrical or photonic circuits.
The silicon srystal is manufactured as a
cylinder with a diameter of 8-12 inches.This
cylinder is carefully sawed in to thin disks
called wafers, which are later polished and
maeked for crystal orientation.
10. This process transforms polycrystalline
silicon in to samples with a singular crystal
orientation, known as ingots.
The polysilicon is mechanically broken in to 1
to 3 inch chunks & undergo etching and
cleaning
These chunks are then packed in to quartz
crucibles for meltdown in cz furnace.
11. A monocrystaline silicon seed is installed in
to a seed shaft in the upper chamber of
furnace.It dips 2mm in to silicon melt.
The seed is slowly get retracted from surface
allowing melt to soldify at the boundary.
Cz furnace Must be Very stable and isolated
from vibrations.
12. Once proper crystal diameter is achieved, the
seed lift is increased.
Gradual cooling allows crystal lattice to
stabilize and makes handling easier before
transport to the next operation.
13. It involves a series of precise mechanical and
chemical processing steps.
The method is called multi- wire sawing
MWS:A thin wire is arranged over cylindrical
spools so that hundreds of parallel wire
segments simultaneously travel through ingot
While the saw as a whole slowly moves
through ingot, the individual wire segments
conduct a translation motion always bringing
fresh wire in contact with silicon
14. It is also called lapping
It create flatness followed by a chemical etch
to create smoothness
Lapping the wafers removes saw marks and
surface defects from front and backside of
wafer.
Edge rounding is normally done before or
after lapping and is very important to the
structural integrity of wafer.
The edges of 200 and 300 mm wafers are
rounded
15. The individual ic of a wafer are tested for
functional defects in a single step before sent
in to prepared matrix.
Wafer tests are carried out by a device called
wafer prober and most commonly used is
probably wafer prober test.
18. Contaminants found on silicon wafer can
have various adverse effects that can
compromise the quality of the wafer.
Contaminants like carbon, iron, cobalt and
copper can cause poor device performance,
electrical degradation, surface roughing and
thin oxide breakdown on gate dielecrics.
Ion contaminants cause device degradation,
elecrical malfunctioning and yield losses.
19. High concentration of ions during epitaxial
silicon layer growth can lead to twinning
dislocation , crystal defects.
Heavy metal contaminants can affects
uncontrolled drifts in the surface of he
semiconductor potential and impacts surface
minority -carriers lifetime.