Design and Implement 8 bit full adder in Xilinx software

1. 2
Problem Statement:
Design the hardware of an “8-bit Full Adder” using the behavioral Verilog HDL and
demonstrate its complete and correct functioning by simulating your design using the Xilinx
ISE simulator.
Block Diagram Of 8-Bit Adder:
About Xilinx ISE:
Xilinx ISE is a design environment for FPGA products from Xilinx, and is tightly-
coupled to the architecture of such chips, and cannot be used with FPGA products from other
vendors. The Xilinx ISE is primarily used for circuit synthesis and design, while ISIM or
the ModelSim logic simulator is used for system-level testing. Other components shipped
with the Xilinx ISE include the Embedded Development Kit (EDK), a Software
Development Kit (SDK) and ChipScope Pro.
Start Up a Xilinx ISE:
Firstly click a Xilinx ISE and start a new project and a new window is appeared and then
make a new source and select a Verilog file name your project like a eightbitAdder and then
a inputs and output window is appeared and make the suitable inputs exactly for 8-bit Adders
. Now a code is generated and after that you have to verify a structural behavior we design
a Test Bench Code and check or verify. Now simulate and check the result

2. 3
Source Code For 8-Bit Full Adder:
We basically work on a Xilinx Software where we have to design a simple 8-bit full Adder
and check the result on the software Output. We design a simple a 8-Bit Adder code and
check the result .
Code File:

3. 4
Test Bench Code:
We design a Test Bench code to check our code’s simulated functional behavior and also we
put our initial value in test bench and also we put a value which we want to add .

4. 5
More Screen Shot(tb_8bitFA):
Here we give input with 100ns delay and also check the simulated result in the next screen
shots.

5. 6
Simulated Result:
Decimal Results:
Here we check the simulated result which is in decimal and also we see clearly a carry result
and also with 100ns delay.

6. 7
Binary Result:
We also check the result in binary by right click and selecting a binary instead of decimal. So,
we get a simulated result in binary form.

7. 8
Why Sum is Zero when we Add 1 in 255?
Reason:
As maximum bits show in 8’bit system is 255=(11111111)2 as with increment of 1 bit it
become 9’bit number 256=(100000000)2 so we get MSB as carry 1 and remaining 8’bits as
zeros.
Conclusion:
In this lab we study introduction Xilinx software by simply design a 8-bit Full Adder and also
check its simulated result in both decimal and binary digits.