Contenu connexe Similaire à CArcMOOC 03.04 - Gate-level design (20) Plus de Alessandro Bogliolo (20) CArcMOOC 03.04 - Gate-level design2. Carc 03.04
alessandro.bogliolo@uniurb.it
Design metrics
• Area (A)
• Number of gates
• Number of 2-input NANDs
• Number of gates inputs
• Performance
• Propagation time (delay): pin-to-pin, overall (Tp)
• Contamination time: pin-to-pin, overall (Tc)
• Throughput (rate)
• Power
• Static (W)
• Dynamic (W)
9. Carc 03.04
alessandro.bogliolo@uniurb.it
T-D Example: Full adder (1)
• Functional specification:
Cin A B S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
CinABBCinAABCinBACinS ''''''
)''()''(' ABBACinABBACinS
BACinBACinBACinS )'()('
10. Carc 03.04
alessandro.bogliolo@uniurb.it
T-D Example: Full adder (2)
• Functional specification:
Cin A B S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
CinABCinABBCinAABCinCout '''
)(' BACinABCinCout
)(' ABBACinABCinCout
)( BACinABCout
17. Carc 03.04
alessandro.bogliolo@uniurb.it
Carry Lookahead Adder (CLAn)
Observations:
ci = ai*bi + (ai+bi)ci-1 = gi + pi * ci-1
The first term generates the carry out (generate gi = ai*bi)
The second term propagates the carry (propagate pi = ai+bi)
Implementation:
ci = gi + pi (gi-1+pi-1 (gi-2+pi-2( ... (g0+p0*Cin)...)))
ci = gi + pigi-1+pipi-1gi-2+ pipi-1pi-2gi-3 + ... + pipi-1pi-2 ...p0Cin
(2)
(3)
(1)
18. Carc 03.04
alessandro.bogliolo@uniurb.it
Carry Lookahead Adder (CLAn)
Unit delay model
A(CLAn) = A(FA0)+…+A(FAn-1) = A(FA0)+…+O(n2) = O(n3)
Tp(CLAn) = Tp(FA) = O(1)
Tc(CLAn) = Tc(FA0) = O(1)
Rate(CLAn) > 1/Tp(CLAn) = O(1)
Gate delay proportional to the number of inputs
A(CLAn) = A(FA0)+…+A(FAn-1) = A(FA0)+…+O(n2) = O(n3)
Tp(CLAn) = Tp(FAn-1) = O(n)
Tc(CLAn) = Tc(FA0) = O(1)
Rate(CLAn) > 1/Tp(CLAn) = O(1/n)
Actual
A(CLAn) = O(n3)
O(1) < Tp(CLAn) < O(n)
Tc(CLAn) = O(1)
O(1/n) < Rate(CLAn) < O(1)