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Validation Test for IC Digital Design
1. Validation Test for IC Digital Design
Alex Lollio, Global Rotation Engineer
Automotive Products Business Unit
Provence Design Centre, France
Sept, 2013 - Oct, 2013
Project Leader : Denis Parmentier
Project Manager : Andre Mourrier
Program Mentor : Massimo Grasso
COMPANY CONFIDENTIAL
1
2. Digital Design Flow: Validation Test is missing
1.
CADENCE DIGITAL SIMULATION TEST
Digital Pattern
Testing Signal
2.
SIMULATED DUT
Expected Output
VALIDATION TEST
CADENCE “.stil”
file generation
VALIDATION TEST ON DIGITAL
DESIGN IS MISSING
3.
FAILURE ANALISYS
Digital Pattern
Testing Signal
Real DUT Output
REAL DUT
COMPANY CONFIDENTIAL
3. Digital Design Flow: Proposed Validation Test
1.
CADENCE DIGITAL SIMULATION TEST
Digital Pattern
Testing Signal
2.
SIMULATED DUT
Expected Output
PROPOSED VALIDATION TEST
Digital Pattern
Testing Signal
Real DUT Output
REAL DUT
PXI System located
in Provence
Test Passed if Real DUT Output = Expected Output
COMPANY CONFIDENTIAL
4. Project Goal: Testing Application
Digital Pattern
Testing Signal
0$
2k$
DUT
CADENCE “.stil”
file generation
TSSI Converter
“.stil” to “.xml”
0$
CADENCE SIMULATION
Expected
Output
PROPOSED VALIDATION TEST
7k$
?
DUT
LabVIEW application for Generating
and Acquiring the digital data and
make the comparison test
Project Goal: Write LabVIEW application for making the test
COMPANY CONFIDENTIAL
5. PXI System Overview
BANANA
TERMINALS
PXI CHASSIS
HSDIO (NI PXI-6552)
• -2 to 5.5V DIO Channels
• Clock 100MHz
• Internal Memory 8MB
PXI CONTROLLER
COMPANY CONFIDENTIAL
8. Conclusions
• LabVIEW Application for .STIL Digital Testing has been presented
• The LabVIEW Application Source Code has been uploaded to
Provence Server and can be easily modified by everyone
• LabVIEW Classes of 5 working days has been done in Provence
Design Center
• PXI system can be easily upgraded with an analog card in order
to synchronize digital generation with analog acquisition
• Next step is to add to the system the IDDQ testing capability
COMPANY CONFIDENTIAL