- Problem: Design a simple ALU using VHDL capable of performing the operations listed on the table on the left. - The ALU shall be capable of operating on 12-bit, two's complement binary numbers and activate flags for overflow (O), carry (C), zero (Z), and sign (S) conditions. - Operations shall be specified via a 4-bit opcode (OC) fed to the ALU along with the operands. Operands shall be fed to the ALU in the form of 16-bit values in a sequence of one or two cycles, producing results in the next cycle. - Results shall be in the form [status)[result], where [status] is a 4-bit code in the form [OCZS] in the four most significant bits and a 12-bit result in the remaining bits. - Two-operand functions: Require two input cycles. The first cycle feeds operand A aligned in bits 11 down to 0. Bits 15 down to 12 will include a NOP opcode in the form 1111. Operand B shall be fed in the same fashion as operand A, replacing the NOP bits with the opcode of the requested operation. - Specitying a NOP in the 2nd cycle shall produce an error result Your task is to design and simulate this ALU with all flags set and an all ones result - One-operand functions: Operate only on A with opcode - Implement your ALU using VHDL. Simulate its operation specified in the first cycle instead of NOP. Entering a twousing a file-fed testbench. Verify that the ALU produces operand opcode in the 1st cycle causes the operand to be correct results for all supported operations, including the operated on itself. For example, specitying opcode 0011 (MUL) status flags being set correctly for each operation. in the 1 st cycle produces AA=A2 - Your ALU shall be optimized for speed and perlorm each - Flags shall function as follows: operation within a single clock cycle. The multiplication - Overliow (OF): Shall be set when the result of an operation operation should be implemented using a combinational overtlows the range of values that can be represented in the circuit or a pipeline, as appropriate. ALU output. - Carry (CF): Shall be set when an operation generates a carry. - Ensure that the input and output signals are properly out of the most significant bit position. synchronized with the rising edge of the clock signal. - Zero (ZF): shall be set when the result of an operation is zero. - You should provide a report with a brief description of your - Sign (SF): Shall be set when the result of an operation is design, your VHDL code, the simulation results, and a brief negative. discussion of any challenges or issues that you - Example: Adding A=4A6h to B=54Bh encountered during the design process. - Cycle 0: F4A6h - The instructor will provide a file with 256 random test - Cycle 1:054Bh vectors and operations to assess the functionality of your The next cycle (Cycle 2) shall produce the result 19F1 design..

1. - Problem: Design a simple ALU using VHDL capable of performing the operations listed on
the table on the left. - The ALU shall be capable of operating on 12-bit, two's complement binary
numbers and activate flags for overflow (O), carry (C), zero (Z), and sign (S) conditions. -
Operations shall be specified via a 4-bit opcode (OC) fed to the ALU along with the operands.
Operands shall be fed to the ALU in the form of 16-bit values in a sequence of one or two cycles,
producing results in the next cycle. - Results shall be in the form [status)[result], where [status] is
a 4-bit code in the form [OCZS] in the four most significant bits and a 12-bit result in the
remaining bits. - Two-operand functions: Require two input cycles. The first cycle feeds operand
A aligned in bits 11 down to 0. Bits 15 down to 12 will include a NOP opcode in the form 1111.
Operand B shall be fed in the same fashion as operand A, replacing the NOP bits with the
opcode of the requested operation.
- Specitying a NOP in the 2nd cycle shall produce an error result Your task is to design and
simulate this ALU with all flags set and an all ones result - One-operand functions: Operate only
on A with opcode - Implement your ALU using VHDL. Simulate its operation specified in the
first cycle instead of NOP. Entering a twousing a file-fed testbench. Verify that the ALU
produces operand opcode in the 1st cycle causes the operand to be correct results for all
supported operations, including the operated on itself. For example, specitying opcode 0011
(MUL) status flags being set correctly for each operation. in the 1 st cycle produces AA=A2 -
Your ALU shall be optimized for speed and perlorm each - Flags shall function as follows:
operation within a single clock cycle. The multiplication - Overliow (OF): Shall be set when the
result of an operation operation should be implemented using a combinational overtlows the
range of values that can be represented in the circuit or a pipeline, as appropriate. ALU output. -
Carry (CF): Shall be set when an operation generates a carry. - Ensure that the input and output
signals are properly out of the most significant bit position. synchronized with the rising edge of
the clock signal. - Zero (ZF): shall be set when the result of an operation is zero. - You should
provide a report with a brief description of your - Sign (SF): Shall be set when the result of an
operation is design, your VHDL code, the simulation results, and a brief negative. discussion of
any challenges or issues that you - Example: Adding A=4A6h to B=54Bh encountered during the
design process. - Cycle 0: F4A6h - The instructor will provide a file with 256 random test -
Cycle 1:054Bh vectors and operations to assess the functionality of your The next cycle (Cycle
2) shall produce the result 19F1 design.