This document summarizes the design of a 4-bit TIQ (Threshold Inverter Quantization) based CMOS flash analog-to-digital converter (ADC) for system-on-chip applications. The proposed ADC uses two cascaded CMOS inverters as comparators, eliminating the need for high-gain differential input voltage comparators and reference voltages. Simulation results show the ADC achieves high speed of 1 GSample/sec and low power consumption, with differential/integral nonlinearity errors between -0.031 to 0.026/-0.024 to 0.011 LSB respectively. Different encoder designs are also evaluated, showing a fat tree encoder has the lowest delay and power consumption.

1. Aswatha Kumar M. et al. (Eds.): Proceedings of ICAdC, AISC 174, pp. 319–328.
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Design of Low Power High Speed 4-Bit TIQ
Based CMOS Flash ADC
Parvaiz Ahmad Bhat1
and Roohie Naaz Mir2
1
Govt. Women’s Polytechnique, Srinagar, India
b_parvaiz@yahoo.co.in
2
National Institute of Technology Srinagar, 190006, J&K, India
naaz310@yahoo.co.in
Abstract. The analog-to-digital converter (ADC) is an essential part of system-
on-chip (SoC) products because it bridges the gap between the analog physical
world and the digital logical world. In the digital domain, low power and low
voltage requirements are becoming more important issues as the channel length
of MOSFET shrinks below 0.25 sub-micron values. SoC trends force ADCs to
be integrated on the chip with other digital circuits. These trends present new
challenges in ADC circuit design. This paper investigates high speed, low
power, and low voltage CMOS flash ADCs for SoC applications.
The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) tech-
nique that uses two cascaded CMOS inverters as a comparator. The TIQ tech-
nique proposed here has been developed for better implementation in SoC ap-
plications. The preliminary results show that the TIQ flash ADC achieves high
speed, small size, low power consumption, and low voltage operation compared
to other ADCs.
1 Introduction
Semiconductor technology is now approaching 100 nanometer feature size and will
soon be below100 nanometer. This technology trend presents new challenges in ana-
log-digital mixed signal circuit design. A mixed signal circuit must be integrated on a
single chip along with logic and memory circuits to form a system-on-chip. The
mixed signal circuit must operate at fast speeds along with digital logic and memory
circuits; otherwise it becomes a bottleneck to the system.
1.1 Challenges in Designing ADC’s for SOC
The major considerations in designing ADCs for the complete SoC are high speed,
low power, and low voltage. In terms of high speed [1], presently 0.130μm CMOS
technology allows processor speeds in excess of 2.4 GHz. However, the sampling
speed of ADC’s fabricated with an advanced BiCMOS process was around 200 mega
samples per second (MSPS). High speed ADCs with a bipolar process operating up to
1.5 giga samples per second (GSPS) for digital oscilloscopes, digital RF/IF signal
processing, direct RF down-conversion, and radar/ECM systems have also been pro-
duced recently.

2. 320 P.A. Bhat and R.N. Mir
The next challenge is low power consumption. ADC’s should be integrated with
digital circuits on a single chip for the portable devices. All battery powered devices
are now being designed to include low power techniques to prolong the battery life.
Similarly, ADCs need low power architecture or a low power technique. Low voltage
operation is one of the difficult challenges in the mixed signal ICs. The down-scaling
of the minimum channel length to 0.065μm results in the reduction of the power
supply voltage to 0.7 V [6]. A mixed- signal circuit designer faces a great challenge
when designing an ADC that operates at low voltage because of the relatively high
threshold voltage of the transistors. As a result, an ADC should be operated in a small
voltage range.
1.2 Solid State Technology
The type of solid-state technology used to implement the converter also affects the
speed of an ADC [2]. Three different types of solid-state technologies are currently
used for high speed ADC implementations: CMOS technology, bipolar technology,
and Gallium Arsenide (GaAs) technology. GaAs technology is the fastest of the three,
and CMOS technology is the slowest. Bipolar technology allows faster operation and
is compatible with the CMOS technology. However, BiCMOS technology requires
more processing steps and higher cost compared to standard CMOS technology.
Therefore, mixed-signal circuit implementation using only the standard CMOS tech-
nology is the preferred choice for SoC products [7].
The proposed ADC in this work utilizes the Threshold Inverter Quantization (TIQ)
technique that uses two cascaded CMOS inverters as a comparator. The TIQ tech-
nique proposed has been developed for better implementation in SoC applications.
The ADC is designed and simulated in 0.12μm CMOS and operates at
1GSamples/sec. Differential/integral nonlinearity (DNL/INL) errors are between –
0.031 to 0.026 LSB and -0.024 to 0.011LSB, respectively.
The rest of the paper is organized as follows: section 2 describes the related work;
section 3 introduces the proposed design and section 4 presents the ADC architec-
ture; section 5 presents the simulation results. A conclusion is presented in section 6
and the references are listed in the end.
2 Related Work
Most of the researchers investigate techniques to enhance speed or reduce power con-
sumption. [9] presents a 4-bit flash-type ADC suitable for ultra wide band applica-
tions. This design shows low power consumption due to use of transistors with re-
duced dimensions. [11] presents a simple and fast flash ADC using TIQ technique. It
offers higher data conversion rates while maintaining comparable power consumption
levels making t suitable for SoC integration using the standard digital CMOS process.
[3] presents a 4-bit flash ADC for wide band applications. It uses clocked digital
comparators that perform the track/hold function thus avoiding the harmonic and inter
modulation distortion usually seen in high frequency signals. [4] presents an ADC
that uses less number of analog components, small size and low power. It is suitable

3. Design of Low Power High Speed 4-Bit TIQ Based CMOS Flash ADC 321
for integration with DSP core for SoC applications. [10] presents a 4-bit flash ADC
using preamplifiers and comparators to provide fast overdrive recovery. In order to
enhance the speed, analog part of the ADC is fully pipelined.
Our work is aimed at developing the design techniques for Flash ADCs with em-
phasis on high-speed and low-power operation using TIQ as a comparator and com-
paring the performance of proposed ADC using three different types of encoders.
3 Proposed Work – TIQ Flash ADC
We propose high speed CMOS architecture with low power consumption, which is
featuring the Threshold Inverter Quantization (TIQ) technique. Fig. 1 shows the TIQ
schematic diagram. The main advantage of the TIQ based CMOS flash ADC design is
a simpler comparator design. The idea is to use digital inverters as analog voltage
comparators. This eliminates the need for high-gain differential input voltage compa-
rators that are inherently more complex and slower than the digital inverters. The TIQ
flash ADC also eliminates the need of reference voltages, which require a resistor
ladder circuit. This simplicity in the comparator part provides both high speed and
lower power consumption at the same time.
The analog quantization level of digital comparator is the switching threshold vol-
tage of the quantization inverter. It is a reference voltage and is self-determined by
the size ratio of NMOS and PMOS. The internal reference voltage, Vm, is defined as
the input voltage Vin of the quantization inverter when the output voltage VO1 equals
to Vi, where both PMOS and NMOS transistors are in saturation. Fig. 2 shows the
static voltage transfer characteristic (VTC) of the inverter. The voltage Vdd is the
supply voltage of the process. By changing the widths of the PMOS and NMOS de-
vices with a fixed transistor length, we get different threshold voltage. The value of
Vm is expressed in equation (1). All figures will be printed in black and white. All
figures are to be numbered using Arabic numerals. Figures should always be cited in
text in consecutive numerical order. Figure parts should be denoted by lowercase let-
ters (a, b, c, etc.). Each figure should have a concise caption describing accurately
what the figure depicts. Include the captions in the text file of the manuscript, not in
the figure file.
(1)

4. 322 P.A. Bhat and R.N. Mir
Fig. 1. TIQ Comparator Schematic diagram
Fig. 2. Static VTC
4 ADC Architecture
The proposed flash ADC features the threshold inverter quantization (TIQ) technique
for high speed and low power using standard CMOS technology that is compatible
with microprocessor fabrication. Fig. 3 shows the block diagram of the TIQ flash
ADC.

5. Design of Low Power High Speed 4-Bit TIQ Based CMOS Flash ADC 323
Fig. 3. Block Diagram of a TIQ Flash ADC
4.1 TIQ Comparator
TIQ role is to convert an input voltage (Vin) into logic ‘1’ or ‘0’ by comparing a refer-
ence voltage (Vref) with the Vin. If Vin is greater than Vref, the output of the comparator
is ‘1’, otherwise ‘0’. Two cascading CMOS inverters can be used as a comparator for
high speed and low power consumption.
4.2 Gain Booster
Each gain booster consists of two cascading inverters with the same circuit as the
comparator, but the transistor sizes of each gain booster are small and identical. The
gain booster is used to increase voltage gain of the output of a comparator so that it
provides a full digital output voltage swing. The propagation delay's trend is almost
exponentially proportional [5] to the transistor length, but the voltage gain follows a
logarithmic function. Therefore, both propagation delay and voltage gain should be
considered together when we choose the size of the gain booster.
4.3 TC-to-BC Encoder
TIQ comparator array produce a thermometer code (TC), which needs to be converted
into binary code (BC) using TC to BC encoder. Different types of encoder can be
used to perform conversion. In our work we have used three types of encoders namely
Fat tree encoder, ROM based encoder and a simple encoder. Simple encoder directly
converts TC to BC unlike first two, which convert TC to BC in two steps.
5 Simulation Results
In this section, we present experimental results of the 4-bit TIQ flash ADC. The TIQ
flash ADCs have been designed with standard CMOS technology [2] of 120nm with

6. 324 P.A. Bhat and R.N. Mir
ADS 2006A tool. The HSPICE models (BSIM3 level 49) have been used as the stan-
dard library. Table 1 lists the parameters of the 4-bit TIQ based Flash ADC. Figures 4
to 10 show the results of simulations carried out in this work.
5.1 Result Interpretation
Fig. 4. Output for 4-bit TIQ comparator
Fig 4 shows DC simulation results of 15 TIQ comparators and shows the uniformity
of 15 equally spaced invertors threshold voltages calculated from the equation (1)
above.
Fig. 5. Output of Gain Booster
Fig 5 shows the DC simulation results of the gain booster which consists of two
invertors in cascade. Gain Booster is used to increase voltage gain of the output of
comparator so that it provides a full digital output voltage swing with sharp transition.

7. Design of Low Power High Speed 4-Bit TIQ Based CMOS Flash ADC 325
Fig. 6. Digital Output for 4 bit TIQ Flash ADC
Fig 6 shows the digital output of an ADC for the Ramp input which varies from
0.58V to 1.21V. In the figure, Bit 1 is the LSB bit and Bit 4 is the MSB bit.
Fig. 7. Output of a 4-bit TIQ flash ADC with sinusoidal input 20MHz

8. 326 P.A. Bhat and R.N. Mir
Performance chart of Encoders
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Simple Rom Fat Tree
Normalizedvalue
# of Transtor
Delay in nsec
power consumed
Fig. 8. Performance Chart of Different Encoders
Fig. 8 shows the performance chart of different types of encoders used with the
three parameters (no. of transistors delay in nano-seconds) and power consumption in
mWatts. From the figure, it is clear that the delay and the power consumption of fat-
tree based encoder has least delay and power consumption.
DNL plot of 4-bit TIQ ADC
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Output Code
DNL(inLSB)
Series1
Fig. 9. DNL Curve of 4-bit TIQ based Flash ADC
Fig. 9 shows the DNL curve of 4-bit TIQ based ADC. The DNL range is from -
0.031 LSB to + 0.026LSB.

9. Design of Low Power High Speed 4-Bit TIQ Based CMOS Flash ADC 327
INL Plot of 4-bit TIQ ADC
-0.03
-0.025
-0.02
-0.015
-0.01
-0.005
0
0.005
0.01
0.015
0000
0010
0100
0110
1000
1010
1100
1110
Output Code
INL(inLSB)
Fig. 10. INL Curve of 4-bit TIQ based Flash ADC
Fig. 10 shows the INL curve of 4-bit TIQ based ADC. The INL range is from -
0.024 LSB to +0.011LSB.
6 Conclusion and Future Work
A simple and fast flash ADC architecture that uses two cascaded CMOS inverters as a
comparator, called Threshold Inverter Quantization (TIQ) technique, has been devel-
oped. The TIQ flash ADC offers higher data conversion rates while maintaining com-
parable power consumption levels so that it is also highly suitable for the complete
SoC integration using the standard digital CMOS process. The simulation test results
showed that the fat tree encoder outperformed the commonly used ROM type encoder
in terms of speed, power consumption, and area for the 4-bit TIQ flash ADC. As a fu-
ture work we will improve the design in many ways. For low power design it is re-
quired to generate the MOSFET width automatically so that the power consumption
of TIQ comparator block can be further reduced. To achieve high speed as well as
high resolution it is possible to use 4-bit flash ADC in pipelined ADC structure.
Moreover the time interleaved concept can be used to increase speed.
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