1. LOGIC DESIGN
Multiplexers

2. 
A multiplexer has
N control inputs
2N data inputs
1 output

A multiplexer routes (or connects) the
selected data input to the output.
The value of the control inputs determines
the data input that is selected.

3. Data
inputs
Control
input
Z = A′.I0 + A.I1
3

4. MSB
LSB
Z = A′.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3

5. MSB
LSB
Z = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 +
A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3

7. 8-to-1 Multiplexer in VHDL

8. 8-to-1 Multiplexer in VHDL

9. Exercise:
Design an 8-to-1 multiplexer using
4-to-1 and 2-to-1 multiplexers only.
Exercise:
Design a 16-to-1 multiplexer using
4-to-1 multiplexers only.

10. Multiplexer (Bus)