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1.prallelism

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Mahesh Kumar Attri
Mahesh Kumar Attri
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Unit-4 Parallelism Chapter - 9
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Exploitation of Concurrency: ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Instruction Pipeline (sec-9.4) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Four segment CPU Pipeline Fetch Instruction Decode & calculate effective Address Branch? Fetch Operand Execute Instruction Interrupt? Interrupt handling Update PC Empty Pipe Yes No No Yes
Timing of Instruction Pipeline Instruction Step 1 2 3 4 5 6 7 8 9 10 11 12 13 1 FI DA FO EX 2 FI DA FO 3 FI DA 4 FI - - FI DA FO EX 5 - - - FI DA FO EX 6 FI DA FO EX 7 FI DA FO EX
Pipeline Conflicts ,[object Object],[object Object],[object Object]
Instruction-level parallelism (ILP) ,[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The superscalar technique is associated with several identifying characteristics (within a given CPU core): ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Processor Level Parallelism ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object]
Amdahl's law ,[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
 
Basic Page Replacement ,[object Object],[object Object],[object Object],[object Object]
Page Replacement : OPT (Optimal Policy) ,[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
CAO Model Question Paper Unit – 3 ,[object Object],[object Object],[object Object],[object Object]
Modes of transfer (11.4) ,[object Object],[object Object],[object Object],[object Object],[object Object]
Programmed I/O ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Interrupt Initiated IO ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Types of Interrupt ,[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object]
DMA (Direct Memory Access – 11.6 ) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],BR DBUS ABUS CPU RD BG WR
[object Object],Address Bus buffers Address registers Word count Register Control Register DS RS DMA RD Control logic WR BR BG Interrupt DMA Req DMA ACK To IO Device Data Bus buffers Data bus Address bus
CAO Model Question Paper Unit – 4 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

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1.prallelism

  • 1. Unit-4 Parallelism Chapter - 9
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  • 6. Four segment CPU Pipeline Fetch Instruction Decode & calculate effective Address Branch? Fetch Operand Execute Instruction Interrupt? Interrupt handling Update PC Empty Pipe Yes No No Yes
  • 7. Timing of Instruction Pipeline Instruction Step 1 2 3 4 5 6 7 8 9 10 11 12 13 1 FI DA FO EX 2 FI DA FO 3 FI DA 4 FI - - FI DA FO EX 5 - - - FI DA FO EX 6 FI DA FO EX 7 FI DA FO EX
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