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Evolution of personal computing microprocessors and socs
- 1. Evolution of Personal Computing Microprocessors Azmath Moosa M. Tech 1st Year 13304006 Credit Seminar
- 2. 01 10 11 SUB 2, 3 Sum A Carry Full Adder sel B D A Full Subtractor 4:2 MUX Out B B A B Shifter and Logic A Shifter and logic B ALU Instruction Decoder 2002 Architecture by Azmath!
- 3. The Invention • Intel was established as a memory device manufacturer • Nippon Calculating Machine Corporation approached Intel to design 12 custom chips for its new calculator. • Intel suggested a family of just 4 chips – 4004 was one of them
- 4. 4004 to 8085 • 4 bit • 2,300 Transistors • 10um PMOS • Clocked @ 740 kHz 4004 8008 • 8 bit • 3,500 Transistors • 500 kHz • 4,500 Transistors • 6um NMOS • 2 MHz 8080 8085 • 3um depletion type NMOS • 3 MHz
- 5. 8086/80186/88 • 16 bit • Pipelined • 29000 Transistors • 3um process • 5, 8, 10 MHz • Chosen by Fetch Execute
- 6. The PC
- 7. 80286 • 16 bit • Pipelined • 134000 Transistors • 1.5um process • Upto 16 MHz
- 8. 80386 • 32 bit • 275,000 transistors • 1um process technology • 33 MHz
- 9. Has become the standard CPU architecture for the PC platform. All vendors must adhere to this standard to make compatible CPUs for the PC.
- 10. Instruction Set • Includes a specification of the set of opcodes (machine language), and the native commands implemented by a particular processor. • Ex: MMX, 3DNow!, SSE,AVX,AES etc. • Either Hardwired or Microcode routines instruction op1 op2 Integer ALU Micro-op table FP ALU Load/Store Operand Fetch
- 11. Pipeline • • • • Fetches Instructions & Operands from memory Any techniques to optimize fetching can be implemented here Converts Instructions to internal micro-op codes Has to process instructions in order Fetch Decode Frontend • • • • Executes instructions Parallel units that perform same operation can be present Instructions can be processed out of order Any techniques to optimize write back can be implemented here Backend Execute Write to Memory
- 12. The Pentium • Codenamed P5 • Superscaler Architecture • Longer Pipeline • 3.1 Million transistors • 800nm process technology • Upto 233 MHz Prefetch Decode Decode Execute Execute Writeback • Included MMX instruction set
- 13. Pentium Pro • Codenamed P6 • Integrated L2 Cache • Chipset + MemoryController = Northbridge • Iface to ATA, PCI, ISA, BIOS, SuperIO = Southbridge
- 14. P6 Architecture • 10 Stage Pipeline • Branch Predictor, predicts branches and prefetches
- 15. Pentium II/III • 250nm process • 7.5/9.5 Million Transistors • AGP for faster graphics • SSE Instruction Set • 1 Ghz
- 17. Pentium 4 • NetBurst Microarchitecture • 42 Million Transistors • 180nm process technology • SSE Instruction Set • 1.4 to 3.0 Ghz
- 18. NetBurst Architecture • 20 Stage Long Pipeline • Trace Cache • Load operands and store • Que • OoO execution • ALU clocked @ dbl • Hyper Threading • Too long, high power dissipation
- 19. Performance Comparison CONTENT CREATION BENCHMARK Pentium 3 Pentium 4 320 325 330 335 340 345 350 355 360 365
- 20. Core Architecture • 65 nm process • 291 Million Transistors • Shorter, Efficient Pipeline • Wide – Dynamic Execution • Superscaler • Macro-fusion • Advanced Digital Media Boost • 128 bit ALU • Advanced Smart Cache • Smart Memory Access • Execute Disable Bit • HT disabled
- 22. Tick - Tock
- 23. Nehalem Architecture • 45 nm process • 700 million transistors • Shared L3 Cache • Integrated Memory Controller
- 24. • • • • • Improved Loop Stream detector Improved Branch Prediction SSE4+ instruction set Turbo boost HT reintroduced
- 26. SandyBridge Architecture • 32nm process • 1.2 Billion transistors • Ondie - GPU • Ring style on-die interconnect • Aggressive Turbo • AVX instruction set
- 27. • Improved BPU • Micro-OP cache • Wider ALU
- 29. IvyBridge • Tick • 22nm FinFET Transistors
- 30. FinFET Structure
- 32. Haswell Architecture • 1.4 Billion transistors • AVX2 Instruction set • Improved cache bandwidth • Improved GPU & QuickSync
- 33. • • • • Improved BPU Unified decoder queue Wider reorder buffer Wider EU with 2 additional ports • FMA – Fused multiply add Backend
- 35. References 1. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture, [online] Available: http://www.intel.com/products/processor/manuals 2. King, J. ; Quinnell, E. ; Galloway, F. ; Patton, K. ; Seidel, P. ; Dinh, J. ; Hai Bui and Bhowmik, A., "The Floating-Point Unit of the Jaguar x86 Core," in 21st IEEE Symposium on Computer Arithmetic (ARITH), 2013, pp. 7-16. 3. Ibrahim, A.H. ; Abdelhalim, M.B. ; Hussein, H. ; Fahmy, A., "Analysis of x86 instruction set usage for Windows 7 applications," in 2nd International Conference on Computer Technology and Development (ICCTD), 2010, pp. 511-516. 4. PC Architecture, Acid Reviews, [online] 2014, http://acidreviews.blogspot.in/2008/12/pcarchitecture.html (Accessed: 2nd February 2014). 5. Alpert, D. and Avnon, D., "Architecture of the Pentium microprocessor," IEEE Micro, vol. 13, Issue 3, pp. 11-21, 1993. 6. Computer Processor History, Computer Hope, [online] 2014, http://www.computerhope.com/history/processor.htm (Accessed: 2nd February 2014). 7. Gartner Press Release, Gartner Analyst, [online] 2014, http://www.gartner.com/newsroom/id/2610015 (Accessed: 8th February 2014). 8. Intel Processor Number, CPU World, [online] 2014, http://www.cpuworld.com/info/Intel/processor-number.html (Accessed: 9th February 2014).