Evaluation test

http://www.bized.co.uk

Evaluation Test

Prepared by
Alaa Salah Shehata
Mahmoud A. M. Abd El Latif
Mohamed Mohamed Tala’t
Mohamed Salah Mahmoud

Version 02 – October 2011
Copyright 2006 – Biz/ed


Evaluation Test

Answer all questions in the following paper
Questions : 50 Question
Time : 30 minute
Full Mark : 50 degree


Evaluation
Test

Question Choice
1 A
2 B
3 ---
4
5
6
7
8 Answer all questions in the paper
9
10
11
12
13
14
15
16
17
18
19
20


01 http://www.bized.co.uk

A ________ is basically one bit of memory which is updated
Evaluation
when clock signal is high:
Test

A D-Flip Flop

B D-Latch

C T-Flip Flop

D Register

Evaluation Test Copyright 2006 – Biz/ed


True or False : VHDL isEvaluation typed hardware description
strongly
language Test

A True

B False



Evaluation
Gate Level Simulation isTest
done before _____________

A Synthesis

B Functional Simulation

C Place and route

D Configuration



In the code shown below, the rst signal is modeled as__________
Evaluation
Process(clk,rst) Test
Begin
if rst =‟0‟ then
Q<=„0‟;
elsif rising_edge(clk) then
Q<= D;
end if;
End process;

A Synchronous, Active High

B Synchronous Active Low

C Asynchronous Active High

D Asynchronous Active Low



Evaluation
IF/CASE should be inside the body of________
Test

A Entity

B Architecture

C Process

D Package



Evaluation
How many architectures can be associated with an entity?
Test

A One or more

B Should be more than one

C Only one

D none



True or False : any VHDL description must contain at least one
Evaluation
entity Test

A True

B False



Evaluation
______cannot be declared inside process unit
Test

A variables

B signals

C Constants



True or False : VHDL isEvaluation
considered a High Level programming
language Test

A True

B False



True or False : Each statement in the architecture body
Evaluation
executed concurrently.Test

A True

B False



True or False : Each statement is in the process body
Evaluation
executed concurrently.Test

A True

B False



True or False : No difference meaning between variable
Evaluation
assignment and signal assignment.
Test

A True

B False



True or False : An internal signal is declared before the
Evaluation
architecture begin. Test

A True

B False



Evaluation
Which of these is an valid identifier
Test

A _c1

B c_10

C Process

D 1d



process (CLK, CLEAR)
begin
if (CLEAR = '1') then
Evaluation
Q <= '0';
Test
elsif (CLK'event and CLK = '1') then
Q <= D;
end if;
end process;
The above code is the process for which flip flop?

A T_FF

B D_FF

C latch

D None of the above



A VHDL statement used to create repetitive portions of
Evaluation
hardware is a(n) ____ Test

A process

B generate

C instantiation

D architecture



Evaluation
A full adder adds ____ Test

A 2 single bits and one carry bit

B 2 2-bit binary numbers

C 2 4-bit binary numbers

D None of the above



True or False : The output of a Mealy machine can change
Evaluation
any time, regardless of the clock pulse.
Test

A True

B False



Which statement / clause in VHDL can be used to cover
Evaluation
unused states in a state Test
machine?

A unused

B others

C else

D Dont_care



How many flip flops are necessary to design a state machine
Evaluation
with 25 states? Test

A 2

B 25

C 5

D 225



A finite state machine has an output determined only by the
Evaluation
present state of the system is ____.
Test

A Moore machine

B Mealy machine

C Max machine

D Min machine



True or False : The Component Instantiation are concurrent
Evaluation
statements Test

A True

B False



Evaluation
True or False : VHDL is case Sensitive
Test

A True

B False



Evaluation
„„<=‟‟ is______________ Test

A Blocking assignment

B Non-Blocking assignment



We use Internal Signals for: (choose all the apply)
Evaluation
Test

A Internal connections in structural description

B Intermediate calculations

C Avoid illegal port usage situations



Std_logic _vector and Std_logic are performed over
Evaluation
bit_vector and bit because …
Test

A They are “built – in” to language

B They are longer names

C They are case sensitive

D They can represent values other than just 0 and 1 such
as weak pull – up /down and high impedance



True or False : Once the VHDL code has been written, it can be used either to
Evaluation
implement the circuit inTest programmable device or can be submitted to a
a
foundry for fabrication of an ASIC chip

A True

B False



process (A, B) process
begin begin
C <= A and B;Evaluation
Test
C <= A and B;
C <= '1'; Wait on A, B;
end process; C <= 1;
Wait on A, B;
end process;

A Equivalent

B Not-Equivalent



Evaluation
True or False : Sequential statements should be written inside a “process”
Test

A True

B False



Evaluation
Variables are updated_________
Test

A Immediately

B After the process suspends



Evaluation
Signals are updated_________
Test

A Immediately

B After the process suspends



Evaluation
res <= (a and not(b)) or Test
(not(a) and b); this statement is :

A True

B Wrong



Evaluation
VHDL is __________ Test

A Strongly typed language

B Weakly typed language



Evaluation
If data stored in the RAM location pointed by addr ,then add must be :
Test

A Integer

B Std_logic_vector

C Bit_vector



In the previous example ,the first waveform express (clk) and the second
Evaluation
express (input) Test
The last two waves express respectively :

A Moore and Mealy

B Mealy and Moore



To avoid cascaded look – up tables , what types of statements are preferred
Evaluation
for Xilinx FPGA s ? Test

A CASE

B IF/ELSE



Evaluation
True or False : Place and Route is performed before Mapping
Test

A True

B False



component add is
port (
a : in Evaluation
std_logic_vector(7 downto 0);
b Test
: in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0));
end component add;
begin
cmp_add: add port map (open, b_in, open);

A Legal

B illegal;



True or False : All VHDl codes that can be simulated are
Evaluation
synthesizable Test

A True

B False



Evaluation
True or False : The best Group is _____
Test

A Start Group

B Start Group

C Start Group

D Start Group


SIGNAL a : std_logic;
SIGNAL b : std_logic;
Signal C : std_logic_vector(1 downto 0);
….. Evaluation
….. Test
Begin

B <= c(a);

A Legal

B Illegal

C C should be output port to be write



PROCESS (X)
variable a: integer;
type int is range -10 to 10;
Evaluation
variable d: int;
Test
BEGIN
d := a;
END PROCESS;

A Legal

B Illegal



Evaluation
True or False : Record is a Group elements of different types
Test

A True

B False



ARCHITECTURE examp OF attrs IS
Type states is (red, yellow, green);
Evaluation
signal state: states;
Begin Test
Output <= state‟high
End examp;

Then the value of output equal

A red

B yellow

C green



True or False :

Evaluation
Signal data_bus : std_logic_vector(15 downto 0);
Test
data_bus <= (1 | 4 | 7 => '1', 2 | 3 => '0', others => 'Z');

Then the value of data_bus will equal
“ZZZZZZZZ1ZZ100Z1”

A True

B False



ARCHITECTURE examp OF attrs IS
signal state: std_logic_vector(7 downto 0);
Begin Evaluation
Process(clr,clk) Test Process(clr,clk)
begin begin
If reset = „1‟ then If reset = „1‟ then
State<= “10000000”; State<= “10000000”;
Elsif rising_edge(clk) then Elsif rising_edge(clk) then
State <= „0‟ & state; State <= state(0) & state;
End if ; End if ;
End process; End process;

The above 2 processes are equal______

A True

B False



Evaluation
True or False : FPGA is faster than ASIC
Test

A True

B False



Evaluation
True or False : ASIC could be programmable more than time
Test

A True

B False


Signal a,b,c: std_logic := „0‟;
Begin
Process(a) Evaluation
Begin Test
a <= „1‟;
b <= a;
c <= b;
End;
After the Process suspend , the value of b = _______

A 1

B 0



True or False :
Signal count: std_logic_vector(0 to 7
Process(clr,clk) Evaluation )
Test
Variable count: std_logic_vector(0 to 7); Begin
begin Process(clr,clk)
If reset = „1‟ then begin
Count <= “00000000”; If reset = „1‟ then
Elsif rising_edge(clk) then Count <= “00000001”;
Count <= count +1; Elsif rising_edge(clk) then
End if ; Count <= count +1;
End process; End if ;
End process;
After 10 clock cycle the value of count in the last two
process will be equal (the same value)

A True

B False


Evaluation
Test


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