http://www.bized.co.uk

Session 1

Prepared by
Alaa Salah Shehata
Mahmoud A. M. Abd El Latif
Mohamed Mohamed Tala’t
Mohamed Salah Mahmoud

Version 02 – October 2011
Copyright 2006 – Biz/ed


Contents -Introduction to VHDL

- ASIC & FPGA Design flow
1
-How to read and write VHDL code
- Library and package
- Entity
- Basic data types
- Architecture

- Demo no. 1
Using Xilinx and Modelsim tools

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Session 1


Introduction
to VHDL

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Session 1


Designing with Boolean Equations

Boolean equations are impractical for large design containing hundreds of flip flops
because it could result in a huge number of logical equations.

X= A.B

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Session 1


Schematic based design

-Schematic based design expanded the
capabilities of Boolean equations.

-The major drawback of traditional design
methods is the manual translation of design
description into a set of logical equations.

-This step can be entirely eliminated with
hardware description languages (HDLs).

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Session 1


Hardware Description Language [HDL]
Question:
How do we know that we have not made a mistake when
we manually draw a schematic and connect components
to implement a function?

Answer:
By describing the design in a high-level [such as (c,
basic…)] language, we can simulate our design before
we manufacture it. This allows us to catch design errors,
i.e., that the design does not work as we thought it would.

• Simulation guarantees that the design behaves as it
should.
HDL is short for Hardware Description Language

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Session 1


What is VHDL ?

-Very high speed integrated circuit Hardware Description Language

-Early 1980s : It was developed by the U.S. Department of Defense
-1987 : IEEE Std 1076 - 87
-1993 : Added some new features and became IEEE Std 1076 – 93
-1999 : An extension to the language called VHDL – AMS
Analog Mixed Signal extension
-2008: IEEE Std 1076 – 2008 (New features)

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Design Flow

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Session 1


Specifications
ASIC and FPGA Design Flow
System Level
Design

Function
RTL Description
Verification

Gate Level
Synthesis
Simulation

Place
&Route

Fabrication Configuration
ASIC FPGA

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Session 1


ASIC and FPGA Design Flow
Specification is an set of requirements before designing the system

RTL Description Register-Transfer Level (RTL)

Function Verification Does this proposed design do what is intended?

Synthesis Convert RTL description into a H/W.

Placement Deciding where to place all electronic components.

Routing Wiring the placed components

This last two steps depend on the rules and limitations of the manufacturing process.

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Session 1


VHDL Language Scope
There is two types of tools
that deal with VHDL

-Simulation
to test the logic design using simulation
models ―All Language syntax used‘‘

-Synthesis
to convert codes to hardware
―pare of Language syntax used‖

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Session 1


How to read
VHDL code

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Session 1


Library and Package

The first lines that you will find at the top of any project

Library and Packages define special types used in the code;

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Design Units

There are two types of design units in VHDL
–Primary
Not dependent upon other design units
Entity (Interface)
?
How the system will communicate with the outside world

–Secondary
Depends on primary design unit
Architecture (Function )
–What the system should do ?

-No secondary can exist as stand-alone—without the primary
-Whenever the primary design unit changes, the secondary design must be
reanalyzed

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Session 1


Entity

Define ports (inputs and outputs) of the module
i.e the interface of the block

Entity declaration

entity <entity_name> is
port (
<port_name> : <mode> <type>;
<port_name> : <mode> <type>;
…
<port_name> : <mode> <type>
);
End <entity_name> ;

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Entity

- <entity_name> Define the port name
- VHDL is case Insensitive ----- Important Note
- Don‘t start the port name or entity name of the port with Underscore _ or number

- <mode> Define the port direction
IN : Only read from it
OUT : Only write on it
INOUT : read from or write on it (controlled by another signal)

- <type> Define the port data type
--------------------------------------------------------------------------------------------
- Last port has no semicolon ;
- Line Comments started by - -
- Comma , can separate ports with the same type and mode
- A,b : in bit ;

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Session 1


Question

System A is composed of system B,C and D.
Determine the entity of system A?

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Session 1


• Entity of 2-input AND Gate

A
C
B AND Gate
Example
1

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Session 1


Entity of 2-input AND Gate A

C
B AND_GATE
ENTITY AND_GATE IS
port ( a : in BIT;
b : in BIT;
C : out BIT
); -- inputs and outputs of the entity
END ENTITY AND_GATE ;

Important Note
to make a comment in VHDL you can put (--) before any line you need it to be a
comment.

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Session 1


Basic data types
VHDL is strongly typed

BIT STD_LOGIC

0 1 0 1 H L U

Default X W Z - Default
value value

BIT_VECTOR : STD_LOGIC_VECTOR :
1D-array each element of the BIT type 1D-array each element of the STD_LOGIC type

Example: Example:
a : in BIT; a : in STD_LOGIC;
b : in BIT_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0);
c : in BIT_VECTOR (0 to 3); c : in STD_LOGIC_VECTOR(0 to 3);
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Session 1


Basic data types

X Z 0 1 U

Unknown High Strong Strong Unitialized
Impedance Zero One Default value

W - H L

Weak Don‘t Weak Weak
Unknown care One Zero

To define std_logic data type
LIBRARY ieee;
USE ieee.std_logic_1164 .all;

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Session 1


• Entity of 2-input AND Gate
using STD_LOGIC type

A
C
B AND Gate
Example
2

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Session 1


Entity of 2-input AND Gate using STD_LOGIC type

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY AND_GATE IS
port ( a : in STD_LOGIC;
b : in STD_LOGIC;
C : out STD_LOGIC
);
A
C
B AND_GATE

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Session 1


Architecture
Describe the operation (relations between inputs and outputs) of the module
i.e the Body of the block

Architecture declaration

architecture <arch_name> of <entity_name> is
-- architecture declarations
begin
-- architecture body
end <arch_name> ;

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Session 1


Architecture
Non-Blocking assignment <=

c <= a and b ;

Note

-the LHS  Outputs only as we write on it
-the RHS  Inputs only as we read from it
and make operations on it

To assign a value in std_logic or bit type
c <= „0‟; or c <= „1‟;

To assign a value in std_logic_vector or bit_vector type
c <= “10……1001”;

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Session 1


• 2-input AND Gate

A
C
B AND Gate
Example
3

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Session 1


2-input AND Gate

LIBRARY ieee;
A
C
B AND_GATE
ENTITY AND_GATE IS
port ( a : in std_logic;
b : in std_logic;
C : out std_logic
); -- inputs and outputs of the entity

ARCHITECTURE behave OF AND_GATE IS
BEGIN
c <= a and b; --non blocking assignment
END ARCHITECTURE behave;

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Session 1


• N-bits AND Gate

A
C
B AND Gate
Example
4

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Session 1


LIBRARY ieee;
USE ieee.std_logic_arith.all; Libraries & Packages headers

ENTITY and_gate IS
port ( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
Interface definition
C : out std_logic_vector (3 downto 0)
(input/output ports)
);
END ENTITY and_gate ;

ARCHITECTURE behave OF and_gate IS
BEGIN
c<= a and b; Functional/behavioral
END ARCHITECTURE behave; Implementation

Important Note
If we need to use a specific bit in vector C,A or B
If we want to put ‗1‘ onsode 2nd bit in vector C then we say C(1)
ex : c(2) <= ‗1‘;

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Session 1


Using Xilinx and Modelsim tools

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Session 1


Writing code that describe the Entity and Architecture of 2-XOR Gate of 2 bit width,
Simulating it on Modelsim and using Xilinx ISE synthesis tool.

2
A
2
XOR C
2
B

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Session 1


Assignment
Session-1
Read Session-1 Notes carefully to be ready
for the next session‘s QUIZ

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Session 1


Download Session 1 material

Introduction to the course.pdf

Session 1.pdf

Demo 1.txt

Ask for the material through mail
start.courses@gmail.com

Facebook group
start.group@groups.facebook.com

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Session 1


Questions
Session-1

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Session 1


Take Your Notes
Print the slides and take your notes here

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Session 1


See You Next Session

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