4. Technology Impact on CPS Issues 65nm vs 45nm 45nm ,28nm vs 65nm 28nm : 65nm 65nm 45nm 45nm : 65nm Buffer di/dt Ratio Relative Decap Relative ESR Buffer size Decap size Decap is less effective at advanced technologies Advanced technologies show more Di/Dt One die modeling is critical for CPS
5. Concurrent Chip-Package-System Design Zin Package Board Transient Analysis of entire system level PDN network Traditional view of chip is black box or simplistic model Signal Integrity analysis of high speed signals Detail Model of Chip allow concurrent system-package-die SI&PI analysis Impedance Analysis of entire system level PDN network
8. Chip-Package-System (CPS) 1.8V 1.2V Chip Power Model + Package Extraction+ PCB/Board Extraction VRM CHIP 2 Package EMI Noise Power Integrity Thermal Integrity Power Delivery Network Impedance Cost Control (low cost market and/or high volume) Board Board
9. Chip-Package-System (CPS) AC Analysis Dynamic Voltage Drop Red: Chip + Pkg analysis Green: Chip + Pkg+ PCB analysis With Package Model Without Package Model Models of the Chip, Package and PCB are necessary for an accurate result.
10. Chip-Package-System (CPS) EMI/EMC Analysis Package/PCB EMI Map Chip Emissions Necessary to model the noise source (Chip) and propagation medium (Package/PCB) 5th harmonic 2nd harmonic SSO Timing Analysis
11. Model-Based CPS Convergence L Metal R Metal R Pkg L PCB R PCB Leaf Tx Global PDNview VRM C4 PG Bump On die Decap On Boarddecap C Metal C Pkg SoC Designersview PCB/Pkg RLC, S parameter L Metal R Metal Leaf Tx C4 PG Bump On die Decap C Metal PCB Designersview CPM R Pkg L PCB R PCB VRM C4 PG Bump On Boarddecap Chip Power Model C Pkg Only Common reference point
16. Chip Power Model (CPM) CHIP DATA Layout(Early to Sign-off) Library CHIP ANALYSIS Dynamic VectorLess Dynamic VCD Static Chip Power Model Static (Iavg, R) Frequency domain (RLC) Time-domain (I(t), RLC) Modes
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18. Chip Power Model (CPM) Each port (or bump) reflects the current flow associated with that port (or bump) reflecting the on-die activity Parasitics are associated with every port (or bump) Each port (or bump) are coupled with every other port Active Current Signature Passive RC Values
26. Noise in Power Delivery Network (PDN) 4 major noise signatures in PDN High Low Mid High frequency noise: 10’s GHz range Die Local Low frequency noise: MHz range Board Socket Package Global Mid frequency noise: 10’s MHz range Package Die Global Very low frequency noise: kHz range Voltage Regulator Board L,C Global Impact Decaps ~ uFDecaps ~ nFDecap ~0.1pF Chip-Package-Board PDN simulation
27. Chip Power Model - Resonance Aware Default chip simulation is activating all the clock frequencies In Resonance Aware, CPM should focus on a specific stressing frequency Digital Current dB Distributed energy between frequencies Constant Power Mode FFT time freq Digital Current dB More energy around Resonance frequency Resonance Aware Mode FFT time freq
28. When to Consider Resonance? Die cap/unit area can be used to estimate total die capacitance
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30. Chip, package co-verification is done on the package and system side using a detailed chip model that is extracted from the complete die spatial and electrical data
31. Early analysis model of the chip is required for early convergence of the package and system design
