The document discusses a power delivery network (PDN) verification flow to analyze power, noise, and reliability for advanced electronic systems. The flow aims to provide high design failure coverage through early detection of faults and weaknesses, enabling early prototyping and improvement of productivity. It involves checks for design weaknesses, static simulation, scan and gate-level vectorless simulation incorporating package and decap effects to thoroughly test designs under different conditions.
3. May 1, 2013
Missing vias
Un-connected devices & wires
Instance PDN hook up quality
Shorts
Design weakness
check
Check that metal density can supply
the design estimated average current
Check pad’s and power gates count and location
Static
Simulation
Checking the design in maximum peak stress test
Scan
RTL VCD VCD simulation with low effort in preparing the VCD,
state propagation is done by RedHawk
Worst power cycle selection
Gate Level VCD with true timing for maximum real
case simulation and silicon correlation
GL VCD
High coverage in detecting design weaknesses:
High frequency
Simultaneous switching
Poor power grid connectivity
Multi cycle vectorless simulation
Simulating Package and Decaps effect
Guided
Vectorless
D
y
n
a
m
I
c
Requires
package
data
Coverage
Library check
Missing and un-complete inputs
check simulation setting:
Required Frequency for getting a good capture
of the design power
Design inputs
check
Coverage
Coverage
Coverage
Coverage
Coverage
Coverage
Early
Analysis
Early power grid prototyping using Excel2IR
PA RPM interface to RedHawk for early RTL level power estimation
Coverage