1. TEST re-defined
Reduction of test cost for ASICs to the minimum,
using the strength of Asia and Europe
By Gert Jørgensen
VP Sales & Marketing
May 2011
May 4, 2011

2. Content of presentation
1. Short introduction to DELTA
2. Test cost analysis of ASIC projects
3. Test activities needed to optimise QA
4. The DELTA solution to minimise cost
5. Minimise test cost – a case studie • More than 28 years at DELTA
• Master of Science from 1982
• Experience as:
6. Some facts and conclusions - Test engineer
- Quality assurance
- ASIC designer
- Project leader
• Business development (1995)
- Turned DELTA from
consultancy to IC-supplier
• Helps major customers:
- To drive innovations and
technology intro’s
May 4, 2011

3. DELTA Microelectronics
Business:
– ASIC supply chain, from specification/GDSII to silicon
– Full turnkey or individual service
Founded: 1976 Microelectronic Testing
1984 Microelectronic Design
1992 OEM manufacturer
2010 IMEC / TSMC and IBM SVAR
2010 More than 25 mill Chips delivered
2011 GF – Global Solutions EMEA channel partner
Locations: Denmark and UK
Geographical coverage:
Europe incl. Israel
May 4, 2011
DELTA Microelectronics

4. Overview
ASIC mode
• Full turnkey solution
• Customer buys good-tested ICs
• ASIC vendor takes full responsibility
• Higher cost
COT mode
• Customer uses different vendors
• Customer takes full responsibility
• Lower cost
May 4, 2011
DELTA Microelectronics

5. DELTA’s Offering - Predictable Path to Success
One Stop Shop
Spec
Spec/RTL/GDSII to Silicon
Local European partner
Proven experienced team
Flexible entry/exit points
Competitive pricing model
Prototypes to high volume
May 4, 2011
DELTA Microelectronics

6. Test cost analyses
May 4, 2011

7. Test cost in ASIC projects
28 ASIC projects performed during the last 2 years at DELTA
Total Devellopment
Design HW-platform
Design Software 25
Packaging 30
Test and QA
15
Methodes to reduce this section
30
May 4, 2011

8. Electrical test of ASIC activities
Wafer test
Package test
May 4, 2011

9. Physical test system
May 4, 2011

10. Hardware vertical probecard
2 x 2 mm
May 4, 2011

11. Test solution implementation
Phase 1
More information at our Booth
Phase 2
Phase 3
Phase 4
May 4, 2011

12. Now DELTA’s Proposal and Ideas - Road map for lower test cost
Reduction of test cost for ASICs to the
minimum,
using the strength of Asia and Europe
May 4, 2011

13. Testing - different focus in a life-circle of ASIC project
Prototype - First volume - High Volume
Prototype Medium Volume High Volume
Local support, Dedicated project Optimisation for low cost Know-how transfer to
& account manager, Qualification and high volume, Yield Asia in 1 week
testing, Debug, Characterisation, improvement,
Quickest time to results Production-ready
May 4, 2011

14. Case story
A DELTA customer is developing chips for
WLAN and VOIP to mobile phones.
DELTA is test house for the two chips,
and it consist of
Baseband-chip and RF transceiver-chip.
May 4, 2011

15. Test cost reduction
FINAL RESULT
RF chip: 3.940 / h RF chip: 2.450 / h
BB chip: 6.000 / h BB chip: 2.680 / h
HW Origional
investments summer
in Octal for 2010
Octal site on BB BB
Investments 60K EUR Investments 20K EUR
Test engineer Test engineer
Test system Test system
Octal probecard SW : Xpress
data mode After initial
to 93K Tuning RF chip: 3.520 / h
verigy BB chip: 3.802 / h
RF chip: 3.940 / h
BB chip: 3.802 / h
Investments 25K EUR
Test engineer
Test system / software update
May 4, 2011

16. Baseband and RF runs
Baseband runs Octal on Verigy P600
RF runs Quad on Portscale
Number of hours:
• BB 9 mill / 6K = 1.500 hours - P600 hours
• RF 9 mill / 3,9K = 2.300 hours - Portscale hours
In total 3.800 hours - 60% of one test system
Conclusion:
DELTA has the capacity to test 18 mill chips if price and
commitment can be agreed.
May 4, 2011

17. Cost of test versus commitment
BB: 6000 RF: 3900 Total cost
Model 1 250 USD 0,041667 0,063451777 0,105118777
Model 2 200 USD 0,033333 0,050761421 0,084094421
Model 3 175 USD 0,029167 0,044416244 0,073583244
Model 4 145 USD 0,024167 0,03680203 0,060969030
6,1 USD cent per chip set (two devices) depending on commitments
May 4, 2011

18. Conclusions
• For debug and ramp to production the local solution is optimum due to
flexible engineering resources
• You need to obtain prices lower than 161 USD per hour in Asia to beat
local price rates valid for Verigy Portscale
• Asia presents low hourly rate with no throughput commitment –
all the way down to 100 USD
• Local test houses is able to present committed test cost
per device to competitive prices.
Thank you!
May 4, 2011