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SC28C94: Quad Universal Asynchronous Receiver/Transmitter (QUART) ,[object Object]
Introduction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
UART Overview ,[object Object],[object Object],CPU  / MPU  / MCU UART IC Receiver RxD Transmitter TxD RxD TxD Data bus (8 bit) Address bus CTRL bus
SC28C94 Quad UART (QUART) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Block Diagram Bus Buffer Timing Channel C Channel D I/O port Control Counter /Timer X2 X1/CLK D0-D7 Internal Bus DUART CD TxDC RxDC TxDD RxDD I/O[3:0]C I/O[3:0]D Interrupt Arbitration IACKN IRQN Operation Control RDN WRN CEN A0-A5 DACKN Channel A Channel B I/O port Control Counter /Timer TxDA RxDA TxDB RxDB I/O[3:0]A I/O[3:0]B DUART AB
Operation Control Block ,[object Object],[object Object],[object Object],[object Object],Operation Control RDN WRN CEN A0-A5 DACKN Address Decode R/W Control Internal Bus A5:0 Read (RDN=Low) Wrtie (WRN=Low) 00000 Mode Register a (MR0a, MR1a, MR2a) Mode Register a (MR0a, MR1a, MR2a) 001000 Mode Register b (MR0b, MR1b, MR2b) Mode Register b (MR0b, MR1b, MR2b) 010000 Mode Register c (MR0c, MR1c, MR2c) Mode Register c (MR0c, MR1c, MR2c) 011000 Mode Register d (MR0d, MR1d, MR2d) Mode Register d (MR0d, MR1d, MR2d)
Timing Block ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Timing X2 X1/CLK Crystal Oscillator Power Up/down Baud rate Generator Internal Bus
Interrupt Arbitration ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Interrupt Arbitration IACKN IRQN Logic Global Registers Interrupt Control Internal Bus
Channel Blocks ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Wake-Up Mode ,[object Object],[object Object],[object Object],[object Object],[object Object]
Interface to Its Controlling Processor ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Processor SC28C94 CEN RDN WRN IACKN IRQN DACKN A0~A5 D0~D7
UART in GPS Navigation System
UART to Bluetooth Interfacing
Additional Resource ,[object Object],[object Object],[object Object],[object Object],[object Object],Newark Farnell

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SC28C94: Quad Universal Asynchronous Receiver/Transmitter (QUART)

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  • 5. Block Diagram Bus Buffer Timing Channel C Channel D I/O port Control Counter /Timer X2 X1/CLK D0-D7 Internal Bus DUART CD TxDC RxDC TxDD RxDD I/O[3:0]C I/O[3:0]D Interrupt Arbitration IACKN IRQN Operation Control RDN WRN CEN A0-A5 DACKN Channel A Channel B I/O port Control Counter /Timer TxDA RxDA TxDB RxDB I/O[3:0]A I/O[3:0]B DUART AB
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  • 12. UART in GPS Navigation System
  • 13. UART to Bluetooth Interfacing
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