Webinar: Microcontroladores Infineon ARM: PSoC e Traveo II para aplicações automotivas e industriais

1
2021-07-27 Copyright © Infineon Technologies AG 2021. All rights reserved. Infineon Proprietary

PSoC™ & Traveo™ II Microcontrollers
For Automotive Solutions
Marcelo Williams Silva
Product Marketing Director & Business Development for
Automotive and Industrial

Infineon at a glance
Financials Market Position
Business Segments Revenue* Employees*
EMEA
19,100
46,700 employees worldwide
Americas
5,200
Asia/Pacific
22,400
60 R&D locations
19 manufacturing locations**
Revenue Segment Result Segment Result margin
# 1 # 1
Automotive Power Microcontroller
# 3
43%
14%
14%
29%
Industrial Power Control (IPC)
Connected Secure
Systems (CSS)
Power & Sensor
Systems (PSS)
Strategy Analytics,
April 2021
Omdia,
September 2020
*2020 Fiscal Year (as of 30 September 2020)
**as of 1 April 2021
Automotive
(ATV)
8,567
982 1,208 1,353 1,319 1,170
FY 16 FY 17 FY 18 FY 19 FY 20
8,029
7,599
7,063
6,473
13.7%
16.4%
17.8%
17.1%
15.2%
For further information: Infineon Annual Report 2020
Omdia,
March 2021
3

Infineon is a top player in all target markets
Source: Based on or includes research from Omdia,
“Annual 2001-2020 Semiconductor
Market Share Competitive Landscaping Tool –
Q4 2020”, March 2021
4.5%
5.5%
5.8%
8.4%
19.0%
Toshiba
Mitsubishi
STMicro
ON Semi
Infineon
13.2%
10.9%
8.5%
8.3%
7.5%
Infineon
NXP
Renesas
TI
STMicro 12.7%
14.5%
14.6%
16.7%
17.1%
Microchip
STMicro
Infineon
NXP
Renesas
Microcontroller
suppliers
total market in 2020: $17.3bn
Automotive
semiconductors
Power discretes
and modules
Source: Based on or includes research from Strategy
Analytics, "Automotive Semiconductor Vendor
Market Shares", April 2021
Source: Based on or includes research from Omdia,
"Power Semiconductor Market Share Database
– 2020", September 2020
4

Infineon offers a unique portfolio that links the real
and the digital world: “One-Stop-Shop” concept
Real-world
applications
Digitale
Welt
Battery-powered devices
Consumer IoT
5G
Power supplies
Drives
Industrial IoT
Connectivity
Automotive
Sense: sensors Compute: microcontrollers,
memories
Actuate: power semiconductors Connectivity: Wi-Fi, Bluetooth, USB
Coin cell-powered devices
Smart Home
Information and data
about the real world
Value addition and
optimized use of resources
Software
Ecosystem
Digital
world
5

Automotive Megatrends: MCU challenges
Levels
1 - 5
Electrified
Transportation
Totally Connected,
Digitized
Low power to support electrification and digitization of the vehicle
Increasing functionality requires more performance
Sensor proliferation drives ever-increasing need for bandwidth
Safety and security requirements increase
Implications
for PSoC &
Traveo™ II
Autonomy
Connectivity
Electrification
6

7
Infineon Proprietary
Copyright © Infineon Technologies AG 2021. All rights reserved.
2021-05-19
Dependable systems require secure systems, which
always sense! always compute! always act! are always connected! are always powered!
Sense
Dependable Sensors
Interpret & decide
Dependable Computing
specialized
sensor processor
driving domain
controller
sensor fusion
decision making
central gateway
Act
Dependable Actuators
Secure communication and authentication
Dependable power supply and distribution
Dependable Memory
Trust requires dependable systems which are always available

Traveo is Providing Low-Power, Safe & Secure Body
Electronics Solutions
System-Level, Body-Electronics Solution
LED/Lighting and
AFS Control Unit
Central
Gateway
Seat Control Unit
Immobilizer
Engine
Start/Stop Button
TPMS Sensor
(Valve/Tier Mounted)
PEPS/Key/ID
DC/DC Converter
Window/Door
Control Unit
HVAC System
Body Control
Module
1 Source: Gartner, Strategy Analytics, Cypress internal estimates
8

Traveo: Providing Better User Experience with Graphics MCUs
1 Source: Gartner, Strategy Analytics, Infineon internal estimates
Applications enabled by Traveo™ Graphics MCUs
Matrix LED Headlights
HVAC System
Head-up Display (HUD)
Electronic Mirrors
Instrument Cluster
9

10
Copyright © Infineon Technologies AG 2021. All rights reserved.
2021-05-19
One-stop-shop for Automotive HMI & Smart Sensors
Target applications for PSOC 4 and PSOC 4 HV
Door Handle
and Foot-kick Detection
Buttons/Sliders Touchpads Touchscreens
Optical Navigation Capacitive Navigation
Biometrics
and Navigation
Hands-On Detection
Liquid Level Sensing Occupant Detection
Intelligent Battery
Sensors
Smart Ignition Systems
PSoC Target
TrueTouch Target
confidential

Smart Sensors Body & Connectivity Chassis &
Safety
Powertrain &
xEV
ADAS
Driver
Information
& HMI
AURIX™TC3x
Performance
&
Memory
TRAVEO™ III (T3G)
PSoC®, TRAVEO™ & AURIX™ Family Overview Roadmap
Successfully covering the entire range of auto applications
AURIX™ TC3x
› AEC-Q100 Grade 0
› ISO26262 ASIL-D
› High performance ASIL-D/SIL3 multi
core up to 6 CPUs @300Mhz
› Up to 16 MB Flash, 6.9MB SRAM
› Up to 24 LIN,20 CAN, 2 GB eth
AURIX™TC4x
TRAVEO™ II
AUTO PSoC
TRAVEO™ II
› AEC-Q100 Grade 1 (Ta 125°C)
› ISO26262 ASIL-B
› Low Power
› Arm® Cortex™ M based Architecture
› Up to 8MB flash, HSM
› GPU TVII-C (Cluster)
AUTO PSoC ®
› ISO26262 ASIL-B ready
› Low Power
› Arm® Cortex™ M0/M0+ based Architecture
› CapSense®, MagSense™ & Multi-sense
Converter
List of applications shown is not exhaustive but exemplary and meant for orientation!
Usage of MCU lineups is not restricted to the application segments shown.
AURIX™ TC4x
Coming Soon
TRAVEO™ III (T3G)
First samples in 2023
Arm® Tricore®
11

Infineon “One MCU” combined portfolio
Covering the entire range of auto applications
Body & Connectivity Chassis &
Safety
Powertrain
& xEV
ADAS
Driver
Information
› HVAC
› Door Control
› Seat Control
› Access Control
› Sunroof Control
› Lighting
TVII-B-E
› Cluster & Head
Unit (companion)
› Center Information
Display
TVII-C
› Automotive
Lighting
› Digital
Mirror
› HVAC
› Instrument Cluster
› HUD
› Safety Companion
› Braking
› Steering
› Airbag
› Domain
Control
› Engine
› Transmission
› Inverter
› OBC
› xEV
› Transfer case
› Camera
› Lidar
› Radar
› Sensor fusion
TC3x
TC3x and TVII both support:
EVITA full level security, Scalable portfolio, AUTOSAR 4.2, Over-the-Air Update Support
TVII-B-H
› Gateway
› BCM
› Telematics
› TVII-B: AEC-Q100 Grade 1 (Ta 125°C)
› TVII-C: AEC-Q100 Grade 2 (Ta 105°C)
› ISO26262 ASIL-B
› Low Power
› Arm® Cortex™ M-based Architecture
› ISO26262 ASIL-D
› Tricore based architecture
› Gateway
› BDC
› Zone Control
› Telematics
› Lighting
› Wireless
charging
Performance
&
Memory
List of applications shown is not exhaustive but exemplary and meant for orientation!
Usage of MCU lineups is not restricted to the application segments shown.
PSoC™
Automotive
Arm® Tricore®
12

PSoC™, Traveo™ and AURIX™ Features
AURIX™
› AEC-Q100 Grade 0
› ISO26262 ASIL-D
› High performance ASIL-D/SIL3 multi
core up to 6 CPUs
› Up to 16MB Flash, 6.9MB SRAM
› Up to 24 LIN, 20 CAN, 2GB Ethernet
TC38
TC3E
TC39
TC33
TC36
TC37
TVII-B-E-1M
TVII-B-E-2M
TVII-B-H-8M
TVII-B-E-512K
TVII-B-H-4M
TVII-B-E-4M
TVII-C-2D-4M
TVII-C-H-4M
TVII-C-E-2M
› AEC-Q100 Grade 1/2
› ISO26262 ASIL-B
› Dual core Arm M7
› Up to 8MB flash, 1MB SRAM
› 2.5D GPU (TVII-C-2D)
› Low power
Traveo™
TVII-C-2D-6M
› AEC-Q100 Grade 1/2
› ISO26262 ASIL-B
› Single Core Arm M0+
› Up to 384kB flash, 32k SRAM
› Capsense / CAN-FD
› Low power
ATV PSoC™
13

Customer MCU decision flow Aurix™ vs. Traveo™ II and PSoC™
Safety
Requirement
ASILC/D/SIL-3
Yes
No
Customer
Need
AURIX
Traveo
Body
No
Yes
Yes
Internal Memory
requirements:
Performance
>2x350MHz
Flash >8MB
SRAM: >1.5MB
Ta>125°C
Need for low power
Scalability to the low
end at 0.5MB Flash
Traveo
Cluster
Need for Graphic
GPU, LP DDR IF
Yes
Internal Memory
requirements:
Flash <512KB
No
Auto
PSoC
Yes
No
14

Roadmap for upcoming open market launches
TraveoTM II & AUTO PSoC
07
PSoC 4000S
January
06
2021 2022
Q
1
PSoC 4100S Plus
January
Q
2
Q
3
Q
4
TVII-B-H-4M
April
08
TVII-B-H-8M
April
PSoC 4100S Max
September
10
11
12
14
16
13
Q
1
Q
2
Q
3
Q
4
Open Market Launch Production Release
Released
Released
Released
Released
Key
Released
2023
17
Q
1
Q
2
09
15
Q4
2020
TVII-B-E-1M
Released
01
TVII-B-E-2M
Released
03
PSoC 4100S
05
Released
02
PSoC 4100/4200
Released
04
PSoC 4000
Released
15

Traveo™ II Product Lineup &
Roadmap

Low Power
Scalability
Performance
Graphics
Audio
Connectivity
Security
Safety Updatability
4
5
6
1
2
3
2 5
Low Power
› Energy-efficient
Processing Power
Scalability
› Complete Portfolio
› Memory Density
› Package Lineup
› Performance
Performance
› Single Arm® Cortex®-M4
› Dual Arm® Cortex®-M7
› Up to 1500DMIPS
Connectivity
› CAN FD
› 1Gb Ethernet
Security
› Hardware Security Module:
eSHE1, HSM2
› Evita Full
Safety
› ISO 26262 ASIL-B
Updatability
› FOTA3 with RWW4 Flash
› eMMC5
› QSPI/HS-SPI
Graphics
Audio
› 3x Performance of Traveo™
Traveo™: Key Features
1 eSHE: enhanced Secure Hardware Extension
2 HSM: Hardware Security Module
3 FOTA: Firmware update Over The Air
4 RWW: Read While Write
5 embedded Multi Media Card
8
7
6
1
2
3
4 5
Traveo™ II
Family
17

Traveo™ II Body MCU Lineup
Values inside the boxes indicate RAM size
Flash
Memory
Size
Pin Count
64 Pin 80 Pin 100 Pin 144 Pin 176 Pin
BGA
272 Pin
BGA
320 Pin
8MB
4MB
4MB
2MB
1MB
512KB
Entry
High-End
768KB
768KB 768KB
1024KB 1024KB
1024KB
256KB 256KB
768KB
64KB
64KB 64KB
128KB 128KB 128KB 128KB 128KB
256KB 256KB
256KB
512KB 512KB 512KB 512KB
512KB
18

Traveo™ II Body MCU Portfolio
Availability
Status
Production
Sampling
Development
Concept
1
Maximum operating frequency
2
Hardware security module, SHE-only mode
available
3
Clock eXtension Peripheral Interface
4
Package pin count
5
Single or dual core option
6
Time Division Multiplexing
7
Fine pitch Ball Grid Array
8
Optional feature
QQYY
QQYY
Body/Gateway/Infotainment
Traveo II Entry MCU Traveo II High MCU
Peripherals Based on Infineon MXS40 Platform
Performance
CYT3BB/CYT4BB
TVII-B-H-4M
2x Cortex®-M75, 250 MHz1,
ASIL-B, HSM,
4MB Flash, 768KB RAM,
eMMC, Ethernet, I2S/TDM6
100-176-Pins4 TEQFP,
272-ball BGA7
CYT2B7
TVII-B-E-1M
Cortex®
-M4, 160 MHz1
,
ASIL-B, HSM2
,
1MB Flash, 128K RAM
64–176 Pins4
LQFP
CYT2B9
TVII-B-E-2M
Cortex®
-M4, 160 MHz1
,
ASIL-B, HSM2
, CXPI3
64–176 Pins4
LQFP
CYT4BF
TVII-B-H-8M
2x Cortex®-M7, 350 MHz1,
ASIL-B, HSM,
eMMC, Ethernet,
FlexRay8, I2S/TDM6
176-Pins4 TEQFP,
272-ball BGA7,
320-ball BGA
CYT2B6
TVII-B-E-512K
Cortex®
-M4, 80 MHz1
,
ASIL-B, HSM2
,
512KB Flash,
64KB RAM
64-100 Pins4
LQFP
NOW NOW
Q221
Q221
CYT2BL
TVII-B-E-4M
Cortex®
-M4,160 MHz1
,
ASIL-B, HSM2
, CXPI3
4MB Flash, 512KB RAM
64–176 Pins4
LQFP
Q121
Q221
19

CYT2BL Series (Super Set - Entry)
CYT2BL000
Body control module (BCM), HVAC, lighting, and gateway
Applications
› 32-bit MCU Core Systems
‒ 160-MHz Arm® Cortex®-M4 Single
‒ 4MB Flash, 128KB Work Flash and 512KB SRAM and Cortex®-M0+ for Crypto
› 2.7-V to 5.5-V Supply Voltages
› Interfaces
‒ Up to 8-ch CAN FD, up to 8-ch SCB, 12-ch LIN-UART, and 4-ch CXPI controller
› AD Converter
‒ Up to 64-ch, 12-bit with 3x successive approximation ADC (SAR ADC) units
› Timers
‒ Up to 12-ch motor control, 63-ch 16-bit timer/counter/PWM (TCPWM), and
8-ch 32-bit TCPWM
‒ Event Generation Timer
› Packages
‒ 64-pin LQFP, 80-pin LQFP, 100-pin LQFP, 144-pin LQFP, 176-pin LQFP
Features
Datasheet: Contact Sales
Collateral
Sampling: Now Production: Contact Sales
Availability
Traveo™ II Body MCU Family: TVII-B-E-4M
Peripheral
System Control Core Block
Regulators
PLL/FLL
RC Oscillators
LVD/BOD
Power Mode
Management
Real-time Clock
WDT/CSV
Reset
Event Generation
Timer
Boot ROM
Code Flash
SWD/JTAG/
Trace
PPU
Work Flash
SRAM
Crypto
DMA
Cortex-M0+
MPU eFuse
IRQ/NMI
8-ch SCB
SPI/I2C/UART
8-ch
CAN FD
GPIO
Smart I/O
16-bit TCPWM 12-ch LIN-UART
64-ch 12-bit ADC
(3 x SAR ADC)
32-bit TCPWM
16-bit Motor
TCPWM
4-ch CXPI
Controller
Cortex-M4
(Single) FPU
20

CYT4BF Series (Super Set – High End)
Peripheral
PLL/FLL
RC Oscillators
LVD/BOD
Power Mode
Management
Real-time Clock
Regulators
WDT/CSV
Reset
Event Generation
Timer
Cortex-M7
(Dual) FPU Boot ROM
Code Flash
SWD/JTAG/
Trace
PPU
Work Flash
SRAM
Crypto
DMA
Cortex-M0+
MPU
D-Cache
I-Cache
IRQ/NMI
11-ch SCB
SPI/I2C/UART
10-ch
CAN FD
eMMC
eFuse
GPIO
Smart I/O
96-ch 12-bit ADC
(3 x SAR ADC)
32-bit TCPWM
SMIF
Ethernet
FlexRay
16-bit Motor
TCPWM
I2S/TDM
CYT4BF000
Traveo™ II Body MCU Family: TVII-B-H-8M
Body control module (BCM), gateway, and infotainment
Applications
‒ 350-MHz Arm® Cortex®-M7 Dual, I/D-Cache
‒ 8MB Flash, 256KB Work Flash, 1024KB SRAM, and Cortex®-M0+ for Crypto
› 2.7-V to 5.5-V Supply Voltages
› Interfaces
‒ Up to 10-ch CAN FD, up to 11-ch SCB, and 20-ch LIN-UART
‒ eMMC, SMIF (QSPI/HS-SPI), up to 2-ch 10/100/1000-Mbit Ethernet and FlexRay
‒ I2S/TDM with TX 3ch and RX 2ch
› AD Converter
‒ Up to 96-ch, 12-bit with 3x successive approximation ADC (SAR ADC) units
› Timers
‒ Up to 12-ch motor control, 87-ch 16-bit timer/counter/pulse-width modulation
(TCPWM), and 16-ch 32-bit TCPWM
‒ Event Generation Timer
› High-speed I/O at 3.3-V in BGA
‒ Second operation voltage required for 3.3-V I/O
› Packages
‒ 176-pin TEQFP, 272-ball BGA, 320-ball BGA
Features
Datasheet: CYT4BF Series
Collateral
Sampling: Now Production: Contact Sales
Availability
21

CYT4DN Series (Graphics)
CYT4DN00
Instrument cluster + HUD
Applications
‒ 2x 320-MHz Arm® Cortex®-M7 and Cortex®-M0+
‒ 6MB Flash, 896KB RAM, and 128KB Work Flash
‒ 4MB VRAM
› 1.15-V, 1.8-V, 3.3-V, and 5.0-V Supply Voltages
› Interfaces
‒ Ethernet, 4-ch CAN FD, 12-ch SCB, and 2-ch LIN-UART
‒ 2-ch SMIF: 4-ch DDR HS-SPI, 2-ch HyperBus™, or 2-ch Octal-SPI
› Cluster Features
‒ 6-ch SMC + ZPD
‒ 2.5D engine, vector drawing
‒ Video-out: 2-ch (LVDS, RGB)/Video-In: 1-ch (RGB, MIPI)
‒ Sound module, PCM-PWM, I2S, and DAC
› Packages
‒ 327, 500-ball BGA
Features
Traveo™ II Graphics MCU Family: TVII-C-2D-6M
Peripheral
Regulators
PLL/FLL
RC Oscillators
LVD/BOD
Power Mode
Management
Real-time Clock
WDT/CSV
Reset
Wakeup Timer
Boot ROM
Program
Flash
SWD/JTAG/
Trace
PPU
Work Flash
SRAM
Crypto
DMA
Cortex®-M0+
MPU eFuse
Graphics
2-ch CXPI
IRQ/NMI
12-ch SCB
SPI/I2C/UART
4-ch
CAN FD
SMIF
GPIO
Smart I/O
48-ch 12-bit ADC
(1 x SAR ADC)
32-bit TCPWM
Sound
I2S, PCM-PWM
16-bit Motor
TCPWM
Ethernet
Audio-DAC
Datasheet: Contact Sales
Collateral
Availability
Sampling: Now Production: Q3/2021
Cortex-M7
(Dual)
FPU
I-Cache
D-Cache
2.5D Engine Vector Drawing TCON
Video In
1-ch
Command
Sequencer
Signature Unit
Video Out
2-ch
VRAM JPEG Decoder
22

Graphics Subsystem Key Features
› Feature-rich Graphics Engine
– 2D and 2.5D rendering
– High Resolution
– 720p with internal VRAM
› Sophisticated Display Controller
– Resolutions up to 2880x1080
– Arbitrary warping for HUDs
› Safety Features
– Supports ISO 26262 compliance
› Video Capture
– RGB and MIPI-CSI2, two or four lanes with a resolution of up
to 2880 x 1080
› JPEG decoder
– Supports Motion JPEG
› Flexible memory interface
– Supports latest high-speed serial memories
› Backward compatible with Traveo™
– Rendering in legacy Image-Based Operation (IBO) mode
– Porting guide (Graphics Driver User Guide)
Traveo II Graphics Subsystem
Graphics Engine Display Control
Internal VRAM
4MB (maximum)
External Memory
Control
Safety Features
JPEG decoder
Video Capture
High Resolution Graphics Engine with Internal VRAM
23

Traveo™ II: Power Mode Characteristics
› TraveoTM II supports six power modes
Active: CPU runs at full frequency with everything turned on
Sleep: CPU clock stops with memories and peripherals turned on
Low-Power Active: CPU runs at low (8 MHz) frequency with PLL, oscillators, and flash turned off
Low-Power Sleep: CPU clock stops with PLL, oscillators, and flash turned off, and system runs at low frequency (8 MHz)
DeepSleep: CPU, SRAM, and high-speed peripherals are in retention and a subset of functions operate
using a 32.768-kHz internal low-speed oscillator
Hibernate: Lowest power mode with no memory or logic retention
Active DeepSleep Hibernate
CPU On Sleep Off
Flash On Off Off
System RAM On Retention Off
Peripheral On Retention Off
Port On On/Freeze Freeze
Real Time Clock (RTC) On On (option) On (option)
Wake-Up Event — Interrupt/Port Input Reset
Power Consumption
70105 mA (M4, 160 MHz maximum)
200 mA (M7, 200 MHz maximum)
35 µA (typical)
64KB SRAM (retained)
5 µA (typical)
24

Traveo™ II: Smart I/O™
› Traveo™ II Smart I/O signal paths allow you to:
Observe I/O input signals directly and control I/O output signals directly
Operate on and modify HSIOM1/DSI2 output signals and route the modified signals to HSIOM/DSI
input signals
Operate on and modify HSIOM/DSI output signals and route the modified signals to I/O output signals
This signal path can be used to change the polarity of a SPI master slave select signal
Operate on and modify I/O input signals and route the modified signals to HSIOM/DSI input signals
This signal path can be used to change the polarity of a SPI slave select signal
1 High-speed I/O matrix, connecting I/O cells to the various digital blocks
Smart I/O I/O Port
HSIOM
HSIOM/DSI
Input Signal
HSIOM/DSI
Output
Signal
I/O Cell
I/O Cell
Input Signal
From 8 I/O
Cells
Output
Signal to 8
I/O Cells
2 Programmable digital subsystem
interface
25

Traveo™ II: SMC: Stepper Motor Control for Dials and Gauges
› Traveo™ II provides up to six SMC channels
– Two motor coils can be connected directly to the four
outputs per channel
– Includes four high-current drivers
› Each SMC uses two TCPWM pulse generators
– 10-bit/8-bit software-selectable operation modes
– Output slew rate control for system noise management
› Other features include:
– Low-power mode
– Variable clock prescaler
– Zero-point detection via ADC
Traveo II MCU
SMC1 SMC4
PWM1P1
PWM1M1
PWM2M1
PWM2P1
PWM1P4
PWM1M4
PWM2M4
PWM2P4
SMC5
SMC2
PWM1P2
PWM1M2
PWM2M2
PWM2P2
PWM1P5
PWM1M5
PWM2M5
PWM2P5
SMC0 SMC3
PWM1P0
PWM1M0
PWM2M0
PWM2P0
PWM1P3
PWM1M3
PWM2M3
PWM2P3
Fuel
Temperature
RPM
Speed
Optional
Optional
26

› Ethernet
– 10/100/1000 Mbps Ethernet MAC compatible with IEEE 802.3
– Support of MII, RMII, and RGMII PHYs
– DMA interface
– Supports Ethernet AVB and integrates Fractional PLL for
clock synchronization
Traveo™ II: CAN, LIN, Ethernet – Automotive networks
› CAN-FD
– Proven compliance to ISO11898-1
– Maximum 8 Mbps supported
– Fully retained in DeepSleep mode
– Shared message RAM with ECC protection
– DMA access to receive FIFOs
› LIN
– LIN protocol support in hardware according to ISO 17987
– Master and slave functionality
– Autonomous header transmission/reception
– Autonomous response transmission and reception
– Message buffer for PID, data, and checksum fields
– Revision 2.1 LIN protocol supported
– Master and slave systems supported
– Hardware assist function Ethernet AVB
7.1ch Audio
stream
PHY
Ethernet MAC
Time
Stamp
Unit
Driver
Protocol stack
AVB
stack
Audio Player
RAM
Fractional
N PLL
I2S/TDM
DMA
DMA
Clock
synchronization
Infineon Supports State-of-the-art In-Vehicle Communication
27

Traveo™ II: Automotive Security
› ADAS, autonomous driving, and new digital service models require
authentication and secure communication
› Traveo™ II integrates HSM to support secure applications
Connected car at security risk
› Wiretapping
› Disguised identity
› Privacy/identity theft
› Unauthorized feature activation
› Unauthorized tuning
› Unlocking speed limit
› Forgery of driving record
› Hardware/property theft
› Manipulation of safety mechanism
Traveo™ II Keeps Connected Car Secure
28

Traveo™ II HSM for Security
› Root-of-Trust boot ROM and Chain-of-Trust boot firmware
› Ensure establishment of hardware isolation between secure and non-secure applications
› Enable fast authentication of ECU software during secure boot
› Flexible configuration of secure domain for efficient resource utilization
› Generation and storage of device-unique secret AES keys
› HSM Performance Library (HSMLib)
› Supports third-party HSM software from established vendors
› Offers comprehensive cryptographic function set for Traveo II
› Enables lowest latency hardware-accelerated crypto operations
Traveo II
HSM
Crypto HW Accelerator
and Cortex-M0+ CPU
Connecting
Device Secure
Communication
Secure and Authenticated Boot
Protection of Keys and Certificates
Firmware Authentication for FOTA
Application
Cores
Cortex®-M4/M7 CPU
Secure
Communication
29

10011010111
Extra-vehicle/In-vehicle Network
CAN-FD
Ethernet
Cloud Gateway HVAC System
Dual Bank Flash
for storing both
the updated
image and
rollback image
with Read While
Write operation
Autosar SecOC3
1 HTTPS: Hypertext Transfer Protocol Secure
2 TLS: Transport Layer Security
3 SecOC: Secure Onboard Communication
External memory
interface for storing
update image
HSM for OTA client,
secure communication,
and authentication of
the updated image
Traveo™ II Use Case: Firmware Over-The-Air (FOTA) Update
HTTPS1/TLS2
Body Control Module
HSM for secure
communication
and Flash loader
Secure high-speed
bulk data transfer
Traveo II HSM Protects FOTA and Assures Authenticity
Traveo II
Family
Traveo II
Family
Traveo II
Family
Traveo II
Family
Traveo II
Family
Traveo II
Family
30

Traveo™ II Use Case: True FOTA
› True FOTA support means:
– Update of the software image in the background
– No interruption of service
– Not recognized by the user
– Roll-back in case of failure
› True FOTA requires:
– Dual-bank memory support
– Read-while-write memory, allowing execution of
software (read) while programming (write)
– HSM-Level Security
Traveo II
Cortex®-M4/M7
CPU
Crypto
Cortex®-M0+
RWW Flash
Bank #2
RWW Flash
Bank #1
Ethernet
CAN FD
31

Protect
Peripherals
/Registers
Traveo™ II: Functional Safety A Holistic System-level Approach
› Traveo II is an ISO 26262 Safety-Element-Out-of-Context product
› Traveo II supports safety critical applications up to ASIL-B
› Traveo II software is developed according to ISO 26262
› Traveo II is supplemented by safety documents
RAM ECC
Flash ECC
(S)MPU
Clock
Supervisor
Window
Watchdog
Timer
Supply
Monitoring
Bus Test
SECDED
Memory
Protection
SECDED
Detect
CPU
Hang-up
Detect
Clock
Failures
Detect
Power
Failures
Fault
Reporting
Structure
PPU
Calculate
Checksum
Manage
Errors
ADC
SelfTest
Security
Function
Signature
Unit
Supervise
Displays
STL
CoreTest
RAMTest
FlashTest
MCAL
Safety Manual
Signature Unit Driver
Safety Analysis Report
Traveo II Family
Traveo II
Auto MCU
Traveo II Offers Safety Hardware, Software, and Documents
32

Functional Safety with Traveo™ II
› Infineon provides the following support for enabling safe applications with Traveo II
› These documents help to achieve functional safety at the system level
› Requirements have been derived to detect potential failure modes and to achieve the hardware
architectural metrics for ASIL-B
HW Safety
Manual
FMEDAs
for individual
Traveo II
products
SW Products
including safety
documentation
33

Traveo™ II: Comprehensive Tools, Kits, and Software
› Software
– Header files and sample driver libraries (SDL)
– AUTOSAR MCAL 4.2.x
– HSM Performance Library
– Graphics Driver
› Third-party software IDEs
– Green Hills Multi and IAR Embedded Workbench
› Third-party debug hardware
– Green Hills and SuperTrace Probe
– IAR I-jet debugging for Arm® Cortex®-M
– Lauterbach
› Hardware
– CPU board
› Functional safety
– Hardware safety manual
– FMEDAs
› Third-party HMI tools
› Other support from Infineon
– SPICE-verified software services and JTAG Flash
programming
CPU board
Extensive Infineon and Partner Development Resources Simplify System Integration
35

Compiler/Programmer/Debugger/Probes for Traveo™ II
Vendor SW Tool Compiler Programmer Debugger
ETM Trace
via SWD/JTAG1)
Trace via TPIU
(4 pins)
Debugger I/F
Infineon Infineon
Programmer 2.1
No MiniProg4,
J-Link(Segger)
No No No SWD/JTAG
IAR IAR Embedded
Workbench
Yes I-jet No SWD/JTAG
IAR IAR Embedded
Workbench
Yes I-jet trace SWD/JTAG/TPIU
Lauterbach PowerView No2 µTrace SWD/JTAG/TPIU
Lauterbach PowerView No2 PowerDebug USB 3 + Cortex®-M debug cable combined with
CombiProbe
SWD/JTAG/TPIU
Lauterbach PowerView No2 PowerDebug Pro + Cortex®-M debug cable combined with
CombiProbe
SWD/JTAG/TPIU
Green Hills Software Multi Yes Green Hills Probe No SWD/JTAG
Green Hills Software Multi Yes Green Hills SuperTrace Probe SWD/JTAG/TPIU
iSYSTEM WinIDEA No2 iC5000 SWD/JTAG/TPIU
iSYSTEM WinIDEA No2 iC5700 SWD/JTAG/TPIU
Dts Insight microVIEW-PLUS Arm DS
MDK-ARM
adviceXross
NETIMPRES
adviceXross SWD/JTAG/TPIU
1 Check with the tool vendor for the exact trace support feature and the latest status of handling of TVII MCUs
2 Vendor does not offer own compiler
36

CYTVII-B-E-1M-SK - Traveo™ II Evaluation Hardware
Size Description
PCB Width ~52 mm (± 5 mm)
PCB Length ~113 mm (± 5 mm)
Component Description
Reset Button
Manual reset without reset controller IC. When button is pushed, reset level is
low. Device reset is active low
System LEDs
Green LED
Power monitor
Current Measurement
Jumper
Measure current consumption of the MCU only (100-mil size, No mount)
Power Supply USB bus power
Power Switch None
ETM Connector None
JTAG Debug
Connector
USB connects IAR I-jet tools for device program and debug.
Header (No mount) connects GHS Multi, Lauterbach, and iSYSTEM tools for
device program and debug
MiniProg3 Connector Samtec FTSH-105-01-L-DV-K (No mount)
Main Crystal
Oscillators with Socket
16-MHz crystals (No mount)
1. MIPI-20 (No mount)
20-pin Cortex® Debug + ETM Connector
1
37

Example:
CYTVII-B-E-1M-176 Evaluation Kit - Traveo™ II Evaluation Hardware
CYTVII-B-E-1M-176-EVK components
› CPU Board (CYTVII-B-E-1M-176-CPU – board without socket)
− Minimal functionality (JTAG, oscillator, etc.)
− Different CPU boards for each package variant
− CPU board optionally available with socket (CYTVII-B-E-176-SO)
− Socket boards can be used for other TVII-B-E products in the same package
› Base Board (CYTVII-B-E-BB)
− Reuse targeted for the entire TVII-B family
− Provides all required analog and digital system resources
− Transceiver for CAN/LIN
CYTVII-B-E-1M-176-EVK
CYTVII-B-E-1M-176-CPU
or CYTVII-B-E-176-SO
CYTVII-B-E-BB
38

CYTVII-B-H-8M-320-CPU & CYTVII-B-8M-320-SO (with socket) -
Traveo™ II Evaluation Hardware
Size Description
Reset Button
Reset controller IC with manual reset. When button is pushed, reset level is low. Device
reset is active low
System LEDs
#3 Green LEDs for power monitoring on 5V, 3V3, and 1V1 rails
#1 Green LED for reset monitoring
Current Measurement
Jumper
Measure current consumption of the MCU only (100-mil size) on each power rail (VDDD,
VDDIO, and VDDA)
Power Supply
12-VDC jack (5.5 mm, 2.1 mm: MJ-179P) and a piggy-back board with Infineon PMIC
(S6BP501A)
Power Switch Control power supply to the board
ETM Connector 38-pin Mictor and MIPI-20 connector for debug and trace
JTAG Debug Connector Arm® Standard-20 and MIPI-10 for debug only
MiniProg4 Connector MIPI-10 to program the MCU
Main Crystal Oscillators
with Socket
16-MHz crystal and socket
Ethernet DP83867IR for Gigabit Ethernet (RJ45) and TJA1100 for Automotive Ethernet (Dsub-9)
Audio Codec TLV320AIC26 for I2S audio, with 3.5-mm audio jack (4-pin)
Serial Memory Interface
(SMIF)
Infineon HyperRAM, HyperFlash, and Dual Quad-SPI Flash, to use SMIF
SD-eMMC Connector To connect to SD-Card or eMMC adapter
USB-UART Transceiver Infineon CY7C65213 for UART logs
Pin Headers To access all MCU pins
1. Mictor 38-pin
Legacy – 38-pin Trace Connector
2. MIPI-20
20-pin Cortex® Debug + ETM Connector
3. MIPI-10
10-pin Cortex® Debug Connector
4. Arm-20
Legacy – 20-pin IDC JTAG Connector
1
2
4
3
39

CYTVII-C-2D-6M-500-CPU - Traveo™ II Cluster CPU Board
Hardware
Size Description
Power Supply
Power supply circuit to generate (1.1 V, 1.8 V, 3.3 V, and 5 V) from PMIC and (1.1 V, 1.5 V,
1.8 V, 2.5 V, and 2.8 V) from LDO
Programming interface
(Arm® Standard JTAG, Cortex® Debug, Cortex® Debug + ETM, and Arm® ETM Mictor) to
connect several programming tools such as IAR I-jet, Green Hills GHS, MiniProg.
USB-UART USB-UART interface for terminal logging (J48).
Reset controller Reset controller with manual reset switch (SW2) and voltage supervision
Jumpers
Measurement of device current on VDDA, VDDD, VDDIO, and VCCD using jumpers J6, J8,
and J10 respectively.
CAN FD Two CAN-FD transceivers based on TJA1057GT (P6, P11).
LIN Two LIN transceivers based on TJA1021T (P1, P2).
user switches
Four user switches (SW3, SW4, SW6, and SW7), hibernate wake switch (SW5), three user
LEDs (LD1, LD2, and LD3), and one potentiometer (VR1) for analog input.
Ethernet Gigabit Ethernet Interface (J64).
Ethernet DP83867IR for Gigabit Ethernet (RJ45) and TJA1100 for Automotive Ethernet (Dsub-9)
Audio interface Audio interface available I2S on J53 and PCM-PWM on J51.
Serial Memory Interface
(SMIF)
HyperFlash and HyperRAM (U19, U20) to use SMIF
Display Interface RGB-OUT (J57 and J67), RGB-CAPTURE (J66) and LVDS (J9 and J10).
MIPI Interface (J42). MIPI Interface (J42).
Pin Headers Pin headers (P3, P4, P5, P7, P8, P9, P10) to access all I/Os of the Traveo II device.
Above picture shows the variant with socket,
usually the board will be sold with soldered MCU.
40

myInfineon Collaboration Platform for Traveo™ II Body
Access to additional technical
documentation:
By registering in the myInfineon
Collaboration Platform (MyICP), you
can get access to add-on technical
documentation, trainings, tools, and
much more for all Traveo II Body
Devices.
32-bit Traveo™ II Automotive
Microcontroller based on ARM® -
Infineon Technologies
41

Supporting Information
https://www.infineon.com/cms/en/product/microcontroller/32-bit-traveo-ii-
automotive-microcontroller-based-on-arm/#!trainings
https://www.infineon.com/cms/en/product/microcontroller/32-bit-traveo-ii-
automotive-microcontroller-based-on-arm/
www.Infineon.com/makers
eLearning
Check out these Links for more Information!
For Further information
Marketing: Marcelo.Williams@Infineon.com
42

Sleek, reliable, low-power capacitive-sensing solutions are difficult to design
› Curved or thick overlays, gloves, and noisy environments reduce signal-to-noise ratio (SNR)performance
› Traditional capacitive sensing solutions require the MCU to remain in an active power mode during an entire scan of the capacitive
sensors, increasing system power consumption
› Features like liquid tolerance require complex algorithms and further complicate system design
› Standard MCUs can interfere with other electronic systems and fail to comply with automotive EMC specifications
Today's HMI systems require features that increase chip count and design complexity, and reduce time to market
› Many sensor-based features require additional analog front ends (AFE) (e.g., opamps), which are not available in standard MCUs
› Adding new features such as digital buffers or combinatorial logic requires external components and prototyping with PCB spins
Cypress' PSoC 4 S-Series MCU solves these problems:
› It delivers Cypress' advance low-power (3uA) CapSense solution that "Just Works" under all conditions with SNR >300:1.
› PSoC Creator™ and its CapSense Components make it easy to design sleek capacitive sensing HMI systems
› Fully compliant PSoC 4 MCUs createan environment free from false touches and radio disturbances
› PSoC 4 MCU configurability enables fast and easy creation of AFEs for sensors, Smart I/Os for rapid prototyping, and CAN
for connectivity, reducing time-to-market
PSoC 4 S-Series MCU solves ATV design challenges
44

The PSoC 4 family of MCUs delivers a broad portfolio for the simplest to the most complex HMI systems
PSoC 4 S-Series MCUs expand the PSoC 4 Portfolio
1 Successive approximation register ADC
2 Maximum number of comparators (including comparators configured using opamps )
3 Average current consumption per sensor
4 Maximum number of hardware-based timers, counters and PWMs, using timer/counter/PWM (TCPWM) blocks and universal digital blocks (UDB)
5 Maximum number of hardware-based SPI, I2C, UART, and LIN Slave interfaces, using SCBs and UDBs
PSoC 4000 PSoC 4000S PSoC4100/4200 PSoC 4100S PSoC 4100S Plus PSoC 4 M-Series PSoC 4100S Max
Flash Size/SRAM 16KB/2KB 32KB/4KB 32KB/4KB 64KB/8KB 128KB/16KB 128KB/16KB 384KB/32KB
DMA Channels 0 0 0 0 8 8 8
ADC
10-bitDel-
Sig @
58 sps
10-bit Single-
Slope ADC
@ 46.8 ksps
12-bit
SAR1
@ 1
Msps
12-bit SAR @1
Msps, 10-bit
Single-Slope ADC
@ 46.8 ksps
12-bit SAR @1
Msps, 10-bit Single-
Slope ADC
@ 46.8 ksps
12-bit
SAR
@ 1
Msps
12-bit
SAR
@ 1
Msps
Opamps 0 0 1 2 2 4 2
Comparators2
1 4 4 4 4 6 2
MHz Crystal Oscillator - - - - Yes - Yes
CapSense 3rd
Generation 4th
Generation 4th
Generation 4th
Generation 4th
Generation 3rd
Generation 5th
Generation
CapSense Avg.
Current3
, SNR
6 μA, >100:1 3 μA, >300:1 6 μA, >100:1 3 μA, >300:1 3 μA, >300:1 6 μA, >100:1 <3 μA, >300:1
UDB Programmable Logic 0 0 4 0 0 4 0
Audio I2S Yes (with UDB) Yes (with UDB) Yes
Timers/Counters/PWMs4
1/1/1 5/5/5 4/4/6 5/5/5 8/8/8 12/12/16 8/8/8
SPI/I2
C/UART/LIN Slave5
0/1/0/0 2/2/2/2 2/2/2/2 3/3/3/2 4/5/5/2 6/4/5/2 4/5/5/2
Crypto (HW
encryption module)
No No No No No No Yes
CAN Controller 0 - 0 - 1 2 1 CAN FD
I/Os, All With CapSense 16 24 24 34 54 51 84
Smart I/Os 0 16 0 16 24 0 24
45

Automotive Portfolio: PSoC® 4
Flexibility | CapSense® | Ease-of-Use
PSoC MCU
PSoC 4000
Intelligent Analog
PSoC 4100
Precision Analog
PSoC 4 HV PA
Prog Digital
PSoC 4200
Sense Anything
PSoC 4700
S = S-Series M = M-Series
7 AEC-Q100: -40C to +105C
1 Flash KB/SRAM KB
2 Comparator
3 Current-output DAC
4 Universal digital block
5 Controller area network
6 AEC-Q100: -40C to +85C
Flash
Sampling Production
Concept Development
QQYY
Industrial
Automotive
Availability QQYY
CY8C4024-S
24-MHz M0+, 16K/2K
CMP, ADC, SCB
IDAC, Smart I/O
Grades: A and S
CY8C4045-S
48-MHz M0+, 32K/4K
CMP, ADC, SCB
IDAC, Smart I/O
Grades: A and S
CY8C4014
16-MHz M0, 16K/2K
CMP, I2C, IDAC
Grades: A and S
CY8C41x8-HVT
48-MHz M0+,256K/32K
NDA ContactSales
CY8C4124
24-MHz M0, 16K/4K
CMP, Opamp, ADC
SCB, IDAC
Grades: A and S
CY8C4125
24-MHz M0, 32K/4K
CMP, Opamp, ADC
SCB, IDAC
Grades: A6 and S7
CY8C4126-M
24-MHz M0, 64K/8K
CMP, Opamp, ADC
SCB, IDAC
Grades: A and S
CY8C4127-M
24-MHz M0, 128K/16K
CMP, Opamp, ADC
SCB, IDAC
Grades: A and S
CY8C4124-S
24-MHz M0+, 16K/2K
CMP, Opamp, ADC
SCB, IDAC, Smart I/O
Grades: A, S and E
CY8C4125-S
24-MHz M0+, 32K/4K
CMP, Opamp, ADC SCB,
IDAC, Smart I/O
Grades: A, S and E
CY8C4126-S
24-MHz M0+, 64K/8K
CMP, Opamp, ADC
SCB, IDAC, Smart I/O
Grades: A, S and E
CY8C4127-S
24-MHz M0+, 128K/16K
CMP, Opamp, ADC
SCB, IDAC, Smart I/O™
Grades: A, S and E
CY8C4146-S
48-MHz M0+, 64K/8K
CMP, Opamp, ADC SCB,
IDAC, Smart I/O
Grades: A, S and E
CY8C4147-S
48-MHz M0+, 128K/16K
CMP, Opamp, ADC, SCB
IDAC, Smart I/O, CAN
Grades: A, S and E
CY8C4149-S
48-MHz M0+, 384K/32K
1
NDA Contact Sales
CY8C41x7-HV
48-MHz M0+, 128K/16K
NDA ContactSales
CY8C4244
48-MHz M0, 16K/4K
CMP, Opamp, ADC
SCB, IDAC, UDB
Grades: A and S
CY8C4245
48-MHz M0, 32K/4K
CMP, Opamp, ADC
SCB, IDAC, UDB
Grades: A and S
CY8C4246-M
48-MHz M0, 64K/8K
CMP, Opamp, ADC
SCB, IDAC, UDB
Grades: A and S
CY8C4247-M
48-MHz M0, 128K/16K
CMP, Opamp, ADC
SCB, IDAC, UDB, CAN
Grades: A, and S
CY8C47xx-S
48-MHz M0+, 32K/4K
NDA Contact Sales
Q420
Q320
46

Family
Package QFN SOIC SSOP TQFP
Pins 24 32 40 48 56 16 20 28 48 48 64 80 100
Body Size (mm) 4 x 4 6 x 6 6 x 6 7x7 8 x 8 3.8 x 9.9 5.3 x 7.3 5.3 x 10.3 7.5 x 15.8 7 x 7 10 x 10 12 x 12 14 x 14
Pitch (mm) 0.5 0.5 0.5 0.6 0.5 1.27 0.65 0.65 0.635 0.5 0.5 0.5 0.5
PSoC 1
21X34  
24X23  
24894 
29X66  
PSoC 4
4000  
41/42XX 
40XXS 1  
41XXS 1 
41XXS Plus 1 
41XXS Max 1  
41/42XXM 1  
47XXS 1 1  
HV 1
1 Wettable flanks package to allow automated optical inspection(AOI)
Automotive PSoC Packages
47

PSoC 4 S-Series enables reliable, low-power ATV designs
1 The ability of a capacitive sensing system to reject large water droplets as false touches on a ground plane that is in proximity to the capacitive sensors
2 A capacitive sensing method that drives a current on a transmit pin and measures the charge on a receive pin; typically used in systems with a large number of closely spaced capacitive sensors
3 A method to detect liquid-level height using capacitive sensors
Power Mode
Current
Consumption
Code
Execution
Digital
Peripherals
Available
Analog
Peripherals
Available
Clock
Sources
Available
Wake-Up
Sources
Wake-Up
Time
Active 2 mA @ 6 MHz Yes All All All - -
Sleep 1.1 mA No All All All
Any interrupt
source
0
Deep-Sleep 2.5 μA No WDT, I2
C POR 32-kHz ILO GPIO, WDT, I2
C 35 μs
Cypress' fourth-generation, low-power CapSense solution provides:
› An average current consumption of 3 μA per sensor (50% improvement over previous CapSense solutions)
› An SNR >300:1 that delivers robust noise immunity and liquid tolerance (3x improvement over previous CapSense solutions)
› Support for grounded-water rejection1 for reliably functioning automotive exterior HMI designs such as door handles
› Support for mutual-capacitance sensing2 to implement advanced features like liquid-level sensing3
PSoC Creator's APIs simplify power management by:
› Enabling changes between power modes
› Controlling the power of individual PSoC Components
48

PSoC Creator simplifies analog front end (AFE) design and saves time on debugging with:
› Analog Components that are dragged and dropped as icons to create custom AFEs
› Component Configuration Tools that simplify parameter configuration with a graphical userinterface
PSoC 4 MCUs integrate AFE designs by delivering:
› Discrete analog performance with a differential 1-Msps, 12-bit SAR ADC, and two high-performance opamps with±1-mV-input
offset voltage and 6-MHz gain bandwidth
› A 1- to 54-channel analog multiplexer (AMUX) that can be flexibly configured to create custom AFE designs
› A 5-V operating voltage that provides over 50% more analog input signal range vs. 3.3 V
Programmable analog blocks easily create custom AFEs
PSoC 4 S-Series Programmable Analog Blocks
12-bit
SAR
ADC
1
Msps
Programmable Analog Blocks
12-bit SAR
ADC
1 Msps
Opamp x2
Low-Power
Comparator x2
CapSense
x1
8-bit IDAC 7-bit IDAC
Opamp Component with Configuration Tool in PSoC Creator
The opamp
graphical
Component
Configuration Tool
simplifies
parameter
configuration
49

PSoC 4 S-Series MCUs further enable rapid prototyping with unique Smart I/Os that:
› Deliver pin-level digital logic functionality with programmable interconnect and routing to implement basic Boolean operations
on I/O signals
› Enable unique capabilities such as digital buffers or combinatorial logic to tasks while keeping the CPU turned off
› Integrate discrete logic like AND and OR gates to reduce system BOM costs and avoid"blue-wires"1
Smart I/Os enable rapid prototyping
Smart I/O
Smart
I/O_1
Smart I/Os configured as digital XOR logic
gates with PWM inputs to implementeight
breathing LEDs
Smart I/Os configured as digital buffers to
provide signal or clock replication of an input
signal from a GPIOpin
Smart I/Os configured as digital OR gates to
implement a priority encoder function2 and that
stores the result in the Smart I/Oregister
Smart I/O
Smart
I/O_1
1 A common practice used during prototyping and debugging to fix or adjust signal inputs and outputs by using external wires on a board
2 A circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs
Smart
I/O_1
Smart I/O
50

Parameter
4th-Gen
(Current)
5th-Gen Improvement Why performance improved
Static IP current 300µA 100µA 3x Removed IDAC and reduced Comparator current
Sensor parasitic capacitance range 5pF - 200pF 5pF – 300pF 1.5x
Converter Resolution VDDA=1.8 V
VDDA = 5.0 V
10 Bit
10 Bit
14 Bit
15 Bit
16x 32x
IDAC 1/f noise dominated previous architecture and
now the comparator dominates. CDAChas only
thermal noise which averages over the conversion.
VDDA sensitivity
Medium
(IDAC PSR) Low (Ratiometric)
10x
Pseudo differential architecture implements fullwave
demodulation which has excellent DC rejection.
Temperature sensitivity
Medium
(Vref, Iref)
Low (Differential, Cref) Yes
Cref has a tiny temp. dependency comparedto Iref
and Vref.
Inductive Max Frequency 2 MHz 20 MHz 10x
We have a new Inductive sensemethod
implemented.
Common mode rejection 56 dB 70 dB
Scan Time (12 Bit scan Typ) 85µs 85µs
PSoC 4100S Max: Why new CapSense Technology?
Significantly Enhanced Performance and Power Consumption
51

PSoC 4 CRYPTO block offers the following cryptography functionalities
› AES1 functionality (block cipher), per FIPS2 197 standard
– Forward block cipher (plaintext to ciphertext) with 128/192/256-bit key
– Inverse block cipher (ciphertext to plaintext) with 128/192/256-bit key
› SHA3 functionality (hash), per FIPS 180-4standard
– SHA1
– SHA224, SHA256
› Cyclic Redundancy Check (CRC) functionality
› Pseudo Random (PR) number generator
› True Random (TR) number generator
› Programmable polynomial of up to 32-bits
PSoC 4100S Max Security features: CRYPTO
1 Advanced Encryption Standard
2 Federal Information Processing Standards
3 Secure Hash Algorithm
52

PSoC® 4000S-Series
PSoC MCU
User interface for infotainment systems, user interface for heating, ventilation, air conditioning
Datasheet: PSoC4000S
Applications
Collateral
Availability
32-Bit MCU Subsystem
› 48-MHz Arm® Cortex®-M0+ CPU
› Up to 32KB Flash
› 4KB SRAM
› Real-time clock (RTC) capability with a watch crystal oscillator (WCO)
› One 10-bit, 46.8-ksps single-slope analog-to-digital converter (ADC)1
› Two low-power comparators (CMP)
› One CapSense® block that supports low-power operation with self- and mutual-capacitance sensing
› Two 7-bit current-output digital-to-analog converters (IDAC) configurable as a single 8-bit IDAC
Programmable Digital Blocks
› Five 16-bit timer/counter/pulse-width modulation (TCPWM) blocks
› Two serial communication blocks (SCB) that are configurable as I2C, SPI, UART or LIN Slave
Packages
› 24-pin QFN and 28-pin SSOP
I/O Subsystem
› Up to 24 GPIOs, including 16 Smart I/Os2
Features
1 A simple ADC used to measure slow-movingsignals
2 Embedded programmable digital logic in the I/Osubsystem
Sampling: Now Production: Now
Programmable
Interconnect
and
Routing
GPIO x8
PSoC® 4 One-ChipSolution
SCB x2
TCPWM x5
GPIO x4
GPIO x2
GPIO x2
Smart
I/O
GPIO x8
Smart
I/O
CMP
x2
7-bit IDAC
x2
Single-
Slope
ADC
CapSense
Advanced
High-Performance
Bus
(AHB)
Flash
(16KB to 32KB)
SRAM
(2KB to 4KB)
WCO
Serial Wire Debug
Cortex®-M0+
48 MHz
MCU Subsystem Programmable Analog
Blocks
I/O Subsystem
Programmable Digital
Blocks
53

PSoC® 4100S-Series
Intelligent Analog
User interface for heating, ventilation, air conditioning, MCU and discrete analog replacement
Datasheet: PSoC 4100S
Applications
Collateral
Availability
› 48-MHz Arm® Cortex®-M0+ CPU
› Up to 64KB Flash
› 8KB SRAM
› Real-time clock (RTC) capability with a watch crystal oscillator (WCO)
› One 12-bit, 1-Msps successive approximation register (SAR) analog-to-digital converter (ADC)
› One 10-bit, 46.8-ksps single-slope ADC1
› Two opamps configurable as programmable gain amplifiers (PGA), comparators, etc.
› One CapSense® block that supports low-power operation with self- and mutual-capacitance sensing
› Five 16-bit timer/counter/pulse-width modulation (TCPWM) blocks
› Three serial communication blocks (SCBs) that are configurable as I2C, SPI, UART or LIN Slave
Packages
› 28-pin SSOP and 40-pin QFN
I/O Subsystem
Features
Programmable
Interconnect
and
Routing
GPIO x8
SCB x3
TCPWM x5
GPIO x8
GPIO x2
GPIO x8
Smart
I/O
GPIO x8
Smart
I/O
CMP
x2
7-bit IDAC
x2
Single-
Slope
ADC
CapSense
Advanced
High-Performance
Bus
(AHB)
Flash
(16KB to 64KB)
SRAM
(4KB to 8KB)
WCO
Serial Wire Debug
Cortex®-M0+
48 MHz
Blocks
I/O Subsystem
Blocks
Opamp
x2
SAR ADC
54

PSoC® 4100S Plus-Series
Intelligent Analog
User interface for HMI applications, Body Control and HVAC applications
Datasheet: ContactSales
Applications
Collateral
Availability
› 48-MHz Arm® Cortex®-M0+ CPU with DMA controller and real-time clock (RTC)
› 128KB Flash and 16KB SRAM
› External MHz oscillator (ECO) with PLL and 32KHz watch crystal oscillator (WCO)
› One 12-bit, 1-Msps successive approximation register (SAR) analog-to-digital converter (ADC)
› One 10-bit, 46.8-ksps single-slope ADC1
› Two opamps configurable as programmable gain amplifiers (PGA), comparators, etc.
› One CapSense® block that supports low-power operation with self- and mutual-
› capacitance sensing
› Eight 16-bit timer/counter/pulse-width modulation (TCPWM) blocks
› Five serial communication blocks (SCBs) that are configurable as I2C, SPI, UART or LIN Slave
One Controller Area Network (CAN) Controller
Packages
› 40-pin QFN and 64-pin TQFP
I/O Subsystem
Features
Programmable
Interconnect
and
Routing
GPIO x8
Segment LCD Drive
TCPWM x8
GPIO x5
GPIO x8
Smart
I/O
GPIO x8
Smart
I/O
CMP
x2
7-bit IDAC
x2
Single-
Slope
ADC
CapSense
Advanced
High-Performance
Bus
(AHB)
Flash
(128KB)
SRAM
(16KB)
Serial Wire Debug
CAN
Cortex®-M0+
48 MHz
Blocks
I/O Subsystem
Blocks
Opamp
x2
SAR ADC
WCO + RTC
DMA
SCB x5
GPIO x8
Smart
I/O
GPIO x8
GPIO x8
55

PSoC 4 HVPA 208k | CY8C41x8-HVPA
Precision Analog (Coming Soon)
Intelligent battery monitoring and management systems
Applications
Collateral
Availability
› 48-MHz Arm® Cortex®-M0+ CPU with DMA controller
› Up to 192KB Code Flash, 16KB Data Flash and 16KB SRAM, with ECC
Security: Advanced cryptographic coprocessor (Crypto) for hardware encryption
Precision Analog Channel Subsystem
› Two 16-bit Precision ΔΣ analog-to-digital converters (ADC)
› Voltage Channel with High-Voltage input divider, Current Channel with automatic Gain
› Temperature and diagnostic channels
› Digital filtering, accumulators, and threshold comparisons on all channels
› Overcurrent comparators with programmable thresholds
Programmable Digital Subsystem
› Four 16-bit timer/counter/pulse-width modulation (TCPWM) blocks
› One independent Local Interconnect Network (LIN) block
› One serial communication blocks (SCB) that are configurable as I2C, SPI, UART or LIN Slave
One Controller Area Network Flexible Data Rate (CAN-FD) Controller
High Voltage Subsystem
› Operates directly off 12 V battery (tolerant up to 42 V), Integrated LIN Transceiver
ASIL-C Compliant1
Packages
› 32-pin Wetable Flank QFN, 48-pin Wetable Flank QFN
I/O Subsystem: GPIOs (up to24)
Features
1 ASIL-C hardware architectural metrics for a typical current sensor application and follows ASIL-C development process
Sampling: Q321 Production: Q222
Programmable
Interconnect
and
Routing
TCPWM x4
Input
MUX
Current
Voltage
Temp
Diagnos-
tics
Advanced
High-Performance
Bus
(AHB)
Code Flash
w/ECC (192KB)
SRAM
w/ECC (16KB)
Cortex®-M0+
24/48 MHz
MCU Subsystem Precision Analog
Channel Subsystem
I/O Subsystem
Subsystem
MPU
LIN
16-bit Delta-
Sigma ADC
Digital
Signal
Processing
Data Flash
w/ECC (16KB)
16-bit Delta-
Sigma ADC
SCB
LDO
High Voltage Subsystem
LIN PHY
Voltage Divider
Crypto
CAN-FD
Serial Wire Debug
DMA
GPIO x8
GPIO x8
GPIO x8
Overcurrent
Comparator
56

PSoC® 4100S Max
Intelligent Analog
User interface for HMI applications, Body Control, and HVAC applications
Applications
Collateral
Availability
› 48MHz Arm® Cortex®-M0+ CPU with a DMA controller
› 384KB flash and 32KB SRAM
› External MHz oscillator (ECO) with PLL and 32KHz watch crystal oscillator (WCO)
› CRYPTO block include AES, TRNG, CRA, PRNG and SHA
› One 12-bit, 1-Msps SAR ADC
› Two opamps configurable as programmable gain amplifiers (PGAs), comparators (CMPs), etc.
› Two low-power comparators
› Two MSC (Multi-Sense Convertor) blocks integrating 5th generation CapSense and MagSense
› Eight 16-bit timer/counter/pulse-width modulator (TCPWM) blocks
› Five serial communication blocks (SCBs) that are configurable as I2C, SPI, or UART
› Segment LCD
› Audio I2S for sound output
One CAN-FD (Controller Area Network with Flexible Data-rate) Controller
Packages
› 48-QFN, 64-TQFP and 100-TQFP
I/O Subsystem
Features
Sampling: Industrial (Q320) Production: Automotive (Q221)
Programmable
Interconnect
and
Routing
PSoC® 4100S Max
SCB x5
AUDIO I2S
GPIO x4
GPIO x8
12-bit SAR
ADC
MSC
x2
Advanced
High-Performance
Bus
(AHB)
WCO
Cortex®-M0+
48 MHz
Blocks
I/O Subsystem
Blocks
CRYPTO
CAN-FD
TCPWM x8
GPIO x8
Smart
I/O
GPIO x8
GPIO x8
Serial Wire Debug
DMA
ECO + PLL
Flash
384KB
SRAM
32KB
CMP
x2
Opamp
x2
Segment LCD
GPIO x8
Smart
I/O
GPIO x8
GPIO x8
GPIO x8
GPIO x8
GPIO x8
Smart
I/O
57

1 12-bit successive approximation register ADC
2 Number of low-power comparators
PSoC 4100S Max MCU Product Selector Guide
3 Timer/counter/PWMblock
4 Serial communication block configurable as UART, SPI, or I2C
Part Number
CPU Speed
(MHz)
Flash
(KB)
Opamps CapSense I2S SAR ADC1 CMP2 TCPWM3 SCB4 CAN FD CRYPTO GPIO Package
CY8C4147AZA-S595 48 128 2 2 X 1000 Ksps 2 8 5 1 X 54 64-TQFP
CY8C4147LDA-S593 48 128 2 2 X 1000 Ksps 2 8 5 1 X 38 48-QFN
This table shows a subset of PSoC 4100S Max Family part numbers. Refer to the PSoC 4100S Max Family datasheet for the complete list.
58

PSoC 4 Part Numbering Decoder
CY 8C 4X X X XX X S XXX
Package:
Flash Size:
CPU Speed:
Product Type:
Marketing Code:
Company ID:
LV = QFN, AZ = TQFP
7 = 128KB, 8 = 256KB, 9 = 384KB
4 = 48 MHz, 2 = 24 MHz
40 = PSoC MCU, 41 = Intelligent Analog
8C = PSoC Platform
CY = Cypress
Device Identification Number That Corresponds to The Part FeatureSet
Series Designator: S = S-Series
Qualification and Temperature Range:
A = Automotive-Qualified, -40C < TA < +85C
S = Automotive-Qualified, -40C < TA < +105C
E = Automotive-Qualified, -40C < TA <+125C
PSoC 4100S Max Product Selector Guide
59

Getting started
1 Fully integrated, easy-to-use Bluetooth Smart modules designed to reduce time-to-market and development costs
$20 PSoC 4100S Plus Prototyping Kit
(CY8CKIT-149)
› Watch the Introduction to PSoC 4 video
› Download the PSoC Creator IDE
› Buy and evaluate the $20 PSoC 4100S Plus Prototyping Kit
› Download the Getting Started With PSoC 4 app note
The PSoC 4100S Plus Prototyping Kit provides:
› CapSense patterns for self-capacitance and mutual-capacitance sensing
› Easy access to all the device I/Os in a breadboard-compatible format
› On-chip system debug with a PSoC 5LP programmer and debugger
› An EZ-BLE PRoC1 Module for Bluetooth connectivity
60

Focus today: system prototyping with standardized footprints
Infineon2Go Arduino Uno
Infineon and 3rd party
breakout boards
1

Three standardized footprints for evaluation boards
for system prototyping
Infineon2Go
Arduino Uno Raspberry Pi
› for MCUs (XMC)
› Motor Control
› Lighting
› Infineon standard mainly for
peripherals (sensors, security
ICs)
› Connection to Arduino Uno /
RaPi footprint via adapters
› Typically optional,
depending on
target application
› Started recently
2

Infineon 2GO layout
+
Microcontroller
XMC2Go(XMC1100)
Security
Shield
Sensor
Kits
https://www.infineon.com/cms/en/tools/landing/infineon-for-makers/shield-2go-my-iot/
TLx493D (16$)
TLI497x
(19$)
TLE4966
(15$) TrustM (10$)
DPS310 (6,9 $) DPS368 (10$) IM69D130 (15$) TrustX (10$)
TLE4964 (12$)
XMC2Go (6$)
Current Sensor Speed Sensor (46$)
H-bridge (15$)
3D magnetic (29$)
Angle Sensor
3D
magnetic
Pressure
current
25A
/
50A
Pressure
waterproof
Hall
latch
MEMS
microphone
Hall
switch
3

Cross-Framework-Platform (XFP) Embedded SW libraries
enabling SW re-use for Infineon‘s embedded HW peripherals
› Quality software libraries for IFX embedded
hardware peripheral ICs
› Support a wide range of embedded use cases
(sw frameworks and hardware platforms)
› Provide an effective IFX development process by
maximizing the reusability and maintainability
of the software tools and its development
infrastructure
More information here
Contact: Enriquez Garcia Juan
Antonio (IFAG DES SDF SCS)
4

Shield2Go adapter for PSoC 6
5

System prototyping – Microcontroller Boards from Infineon
Arduino IDE /Platform.io integrated Arduino Uno layout compatible
XMC4700 Relax (36 $)
XMC4700 Relax Lite (15 $)
XMC1100 Boot Kit (20 $)
XMC4700 Relax Lite (15 $) XMC4700 Relax (36 $)
XMC4300 Relax
EtherCat Kit (73 $)
Hitex ShieldBuddyTC275 (143 $)
Hitex ShieldBuddyTC375 (148 $)
XMC4400 Platform2Go (73,5$)
XMC4200 Platform2Go (63 $)
XMC4400 Platform2Go (73,5 $)
XMC4800 Relax
EtherCat Kit (no price)
XMC2Go (6 $)
6

PSoC 4 Product Webpage
www.cypress.com/PSoC4
Automotive Product Roadmap
www.cypress.com/Automotive/Roadmap
PSoC Creator IDE
www.cypress.com/PSoCCreator
PSoC 4 S-Series Pioneer Kit
www.cypress.com/CY8CKIT-041
App Notes
Getting Started with PSoC 4 (AN79953) www.cypress.com/AN79953
PSoC 4 Low-Power Modes and Power Reduction Techniques (AN86233)
www.cypress.com/AN86233
PSoC 4 CapSense Design Guide (AN85951) www.cypress.com/go/AN85951
References and links
Code Examples
CAN Simplex Communication with CapSense (CE97311)
http://www.cypress.com/documentation/CE97311
Basic LIN Slave Implementation in PSoC 4 (CE96999)
http://www.cypress.com/CE96999
Contact Automotive Marketing
Marcelo.Williams@Infineon.com
61

Webinar: Microcontroladores Infineon ARM: PSoC e Traveo II para aplicações automotivas e industriais

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