Wireless Temperature Measurement with LabVIEW and Spartan3E

Wireless Temperature measurement with LabView FPGA Page 1
I.-ABSTRACT
The goal of this project is the creation of a wireless temperature
measurement system.
For reaching this goal the Xilinx Spartan-3E starter board is used
that contains a FPGA (Field Programmable Gate Array). Normally this
kind of silicon is programmed and reprogrammed in VHDL (VHSIC
Hardware Description Language) but for this project we used a brand
new design tool for this board: “National Instruments LabVIEW FPGA”.
LabVIEW FPGA is a data flow language that let you create
programs by connecting blocks by use of wires. For us technical
engineers this is a programming methodology that is not far away from
our block diagrams that we use for representing technical solutions
and systems.
The temperature sensor in this wireless system is a PT-100 (El-1022)
analog sensor so we did use an ADC (Analog Digital Convertor) to get
the voltage across this sensor in digital form on the chip. This ADC is
connected to the FPGA by mean of an SPI-Interface.
Once the value is in digital form into the FPGA we need to send
over the value of the temperature to the target of this wireless
temperature measurement system. The target of the system was a
standard Host PC. The communication between this HOST PC and the
Xilinx Spartan-3E board is implemented by mean of a ZigBee interface.

II.-PREFACE
OBJECTIVE
The final aim of this project is to know the temperature of a
determinate place and communicate it with another computer with
wireless connection. To make this possible have been employed
different devices, like the PT-100 (El-1022) analog sensor, the Spartan-
3E board with the FPGA chip, Xbee and for the design of the program
we used the National Instruments Labview FPGA.
Therefore, for better understanding of the project, would be
advisable to have knowledge in the Labview FPGA and in electronics.
EXPRESSION OF GRATITUDE
There are much people to whom I would like to express my
gratitude. Expressly to my tutor Vincent Claes, for his help in the project
and also to Patric Hilven. I could not forget Lourdes Dominguez and
Martens Daniels for their help in the first days. I must mention all the
Erasmus students that I have meet here. Moreover, I am very grateful
to my parents Jose Antonio Alonso and Maite Diez de Salazar, without
forget my sister Agurtzane Alonso, for giving me this opportunity.
PETITIONER
The electronics department of XIOS Hogeschool Limburg has
requested this project.
XIOS Hogeschool Limburg.
Universitaire Campus – Gebouw H – Be 3590 Diepenbeek – Belgium.
PERFOMER
The performer of this project is Josu Alonso Diez de Salazar,
student from Euskal Herriko Unibertsitatea – Universidad del Pais Vasco
– University of the Basque Country.

This project has been achieved at XIOS Hogeschool Limburg in
accordance with the Erasmus Exchange program.
STAGES IN THE DEVELOPMENT OF THE PROJECT
WEEK ACTIVITY
1 Arrival to Hasselt. Interview with Vincent Claes and Patrick
Hilven.
2 Introduction to the FPGA and VHDL.
3 Learning VHDL
4 Learning VHDL
5 Learning Labview FPGA
6 Learning Labview FPGA and doing some exercises in the
Spartan-3E
7 Starting with the program
8 Eastern holidays
9 Eastern holidays
10 Program develop
11 Program develop and texting at the Spartan-3E
12 Program develop of the program with the temperature
probe and texting at the board
13 Continuing with the program of the project and texting at
the board
14 Program develop and starting writing thesis
15 Working in EI-1022 interface to the board and writing thesis
16 Working in the develop of the EI-1022 interface to the
board and writing thesis
17 Holidays in Spain
18 Working in the develop of the EI-1022 interface to the
board and writing thesis
19 Carry out the presentation

III.-INTRODUCTION
This project is mainly based on the FPGA technology and in this
case this chip is on the Xilinx Spartan-3E board. For the realization of
the program is used Labview FPGA, but the original programming
language of the chip is VHDL. Therefore, for the better understand, is it
advisable to have, at least, basic knowledge in this programming
language. Because of this, is enclosed a little manual of VHDL.
The FPGA (Field Programmable Gate Array) A type of gate array
that is programmed in the field rather than in a semiconductor.
Containing up to hundreds of thousands of gates, there are a variety
of FPGA architectures on the market. Some are very sophisticated,
including not only programmable logic blocks, but programmable
interconnects and switches between the blocks. The interconnects
take up a lot of FPGA real estate, resulting in a chip with very low gate
density compared to other technologies.
The FPGA technology give to the programmer the possibility to
design the program working in parallel the different parts of it, that is to
say, that could work at the same time. In difference with the most of
the other microcontrollers that works serially.
To measure the temperature, is used the analog temperature
probe PT-100 (El-1022). The program is design, for measure the values
that the sensor is giving, between 0°C and 99°C.
For communicate the values that we get from the probe, to the
FPGA. We must use an ADC (Analog Digital Convertor). The Spartan-
3E Starter Kit board includes a two-channel analog capture circuit,
consisting of a programmable scaling pre-amplifier and an analog-to-

digital converter (ADC). The analog capture circuit converts the
analog voltage on VINA or VINB and converts it to a 14-bit digital
representation, D [13:0], but we will deepen later.
This digital number is transformed and treaties with Labview, to
be send it by the Xbee. For this transformation, there are some
expressions and also we will deepen more later on this because is one
of the important things.
The last part of the project is the wireless communication
between the FPGA and the HyperTerminal of another computer. In
order, to do this possible, we have to transform the numbers into ASCII
code and send it from the Xbee module.
The Xbee (formerly known as Series 2) RF Modules were
engineered to operate within the ZigBee protocol and support the
unique needs of low-cost, low-power wireless sensor networks.

IV. - PROJECT DESCRIPTION
The project has different parts, one experimental and other
programming part. We are going to explain on the following points the
different parts and stages followed on its development.
4.1. - MATERIAL AND METHODS
4.1.1.-SPARTAN-3E STARTER KIT BOARD:

This is one of the most important parts of the project. We use
different devices of the board, the FPGA, the ADC, the Header J2 for
the communication, the flash memory…. Therefore, is important to
start learning something about the operation of the board.
4.1.1.1. -SPARTAN-3E FPGA FEATURES AND EMBEDDED PROCESSING
FUNCTIONS
The Spartan-3E provides a convenient development board for
embedded processing applications. The board highlights these
features:
• Spartan-3E specific features:
1. Parallel NOR Flash configuration
Figure 1

2. MultiBoot FPGA configuration from Parallel NOR Flash PROM
3. SPI serial Flash configuration
• Embedded development
1. MicroBlaze™ 32-bit embedded RISC processor
2. PicoBlaze™ 8-bit embedded controller
3. DDR memory interfaces
4.1.1.2.-KEY COMPONENTS AND FEATURES
The key features of the Spartan-3E Starter Kit board are:
• Xilinx XC3S500E Spartan-3E FPGA
1. Up to 232 user-I/O pins
2. 320-pin FBGA package
3. Over 10,000 logic cells
• Xilinx 4 Mbit Platform Flash configuration PROM
• Xilinx 64-macrocell XC2C64A CoolRunner CPLD
• 64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+
MHz
• 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)
1. FPGA configuration storage
2. MicroBlaze code storage/shadowing
• 16 Mbits of SPI serial Flash (STMicro)
1. FPGA configuration storage
2. MicroBlaze code shadowing
• 2-line, 16-character LCD screen
• PS/2 mouse or keyboard port
• VGA display port
• 10/100 Ethernet PHY (requires Ethernet MAC in FPGA)
• Two 9-pin RS-232 ports (DTE- and DCE-style)
• On-board USB-based FPGA/CPLD download/debug interface
• 50 MHz clock oscillator
• SHA-1 1-wire serial EEPROM for bit stream copy protection
• Hirose FX2 expansion connector
• Three Digilent 6-pin expansion connectors
• Four-output, SPI-based Digital-to-Analog Converter (DAC)

• Two-input, SPI-based Analog-to-Digital Converter (ADC) with
programmable-gain
• pre-amplifier
• ChipScope™ SoftTouch debugging port
• Rotary-encoder with push-button shaft
• Eight discrete LEDs
• Four slide switches
• UG230 (v1.0) March 9, 2006
• Design Trade-Offs R
• Four push-button switches
• SMA clock input
• 8-pin DIP socket for auxiliary clock oscillator
4.1.1.3.-DESIGN
A typical FPGA application uses a single non-volatile memory to
store configuration images. To demonstrate new Spartan-3E
capabilities, the starter kit board has three different configuration
memory sources that all need to function well together.
The voltage for the applications is achieves though a triple-
output regulator developed by Texas Instruments, the TPS75003
specifically to power Spartan-3 and Spartan-3E FPGAs. This regulator is
sufficient for most stand-alone FPGA applications. However, the starter
kit board includes DDR SDRAM, which requires its own high-current
supply. Similarly, the USB-based JTAG download solution requires a
separate 1.8V supply.
The TPS75003 is a complete power management solution for
FPGA, DSP and other multi-supply applications. Independent Enables
for each output allow sequencing to minimize demand on the power
supply at start-up. Soft-start on each supply limits inrush current during
start-up. The TPS75003 is fully specified from –40°C to +85°C.
The PS/2 port on the Spartan-3E Starter Kit board is powered by
5V. Although the Spartan-3E FPGA is not a 5V-tolerant device, it can

communicate with a 5V device using series current-limiting resistors, as
shown in figure 2.
Figure 2
4.1.1.4. FEATURES
• Two 95% Efficient, 3A Buck Controllers and 300mA LDO
• Tested and Endorsed by Xilinx for Powering the Spartan™-3,
Spartan-3E and Spartan-3L FPGAs.
• Adjustable (1.2V to 6.5V for Bucks, 1.0V to 6.5V for LDO) Output
Voltages on All
• Channels
• Input Voltage Range: 2.2V to 6.5V
• Independent Soft-Start for Each Supply
• Independent Enable for Each Supply for Flexible Sequencing
• LDO Stable with 2.2μF Ceramic Output Cap
• Small, Low-Profile 4.5mm x 3.5mm x 0.9mm QFN Package
Like that we could found easily, different sources for other
devices, and for example we use the LCD source for the temperature
probe.

4.1.1.5. –FPGA
4.1.1.5.1.- INTRODUCTION TO THE FPGA
An FPGA is a chip that consists of many unconfigured logic
gates. Unlike the fixed, vendor-defined functionality of an application-
specific integrated circuit (ASIC) chip, you can configure and
reconfigure the FPGA for different applications. FPGAs are used in
applications where the cost of developing and fabricating an ASIC is
prohibitive, or the hardware must be reconfigured after being placed
into service. Because FPGAs can be used for implementation of
custom algorithms in hardware, they offer benefits such as precise
timing and synchronization, rapid decision making, and simultaneous
execution of parallel tasks.
Therefore is interested to know the operation and characteristics
of the FPGA in this board for a better development.
Field-Programmable Gate Arrays (FPGAs) is specifically designed
to meet the needs of high volume, cost-sensitive consumer electronic
applications. The Spartan-3E family builds on the success of the earlier
Spartan-3 family by increasing the amount of logic per I/O,
significantly reducing the cost per logic cell. New features improve
system performance and reduce the cost of configuration.
Because of their exceptionally low cost, Spartan-3E FPGAs are
ideally suited to a wide range of consumer electronics applications,
including broadband access, home networking, display/projection,
and digital television equipment.
The Spartan-3E family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost, the lengthy
development cycles, and the inherent inflexibility of conventional
ASICs. Also, FPGA programmability permits design upgrades in the field
with no hardware replacement necessary, an impossibility with ASICs.

4.1.1.5.2. -FEATURES
• Very low cost, high-performance logic solution for high-volume,
consumer-oriented applications.
• Proven advanced 90-nanometer process technology.
• Multi-voltage, multi-standard SelectIO™ interface pins.
1. Up to 376 I/O pins or 156 differential signal pairs.
2. LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards.
3. 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling.
4. 622+ Mb/s data transfer rate per I/O.
5. True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential
I/O.
6. Enhanced Double Data Rate (DDR) support.
7. DDR SDRAM support up to 333 Mb/s.
• Abundant, flexible logic resources.
1. Densities up to 33,192 logic cells, including optional shift
register or distributed RAM support.
2. Efficient wide multiplexers, wide logic.
3. Fast look-ahead carry logic.
4. Enhanced 18 x 18 multipliers with optional pipeline.
5. IEEE 1149.1/1532 JTAG programming/debug port.
• Hierarchical SelectRAM™ memory architecture.
1. Up to 648 Kbits of fast block RAM.
2. Up to 231 Kbits of efficient distributed RAM.
• Up to eight Digital Clock Managers (DCMs).
1. Clock skew elimination (delay locked loop).
2. Frequency synthesis, multiplication, division.
3. High-resolution phase shifting.
4. Wide frequency range (5 MHz to over 300 MHz).
• Eight global clocks plus eight additional clocks per each half of
device, plus abundant low-skew routing.
• Configuration interface to industry-standard PROMs.
1. Low-cost, space-saving SPI serial Flash PROM.
2. x8 or x8/x16 parallel NOR Flash PROM.
3. Low-cost Xilinx Platform Flash with JTAG.
• Complete Xilinx ISE® and WebPACK™ software.
• MicroBlaze™ and PicoBlaze™ embedded processor cores.
• Fully compliant 32-/64-bit 33 MHz PCI support (66 MHz in some
devices).
• Low-cost QFP and BGA packaging options.

1. Common footprints support easy density migration.
2. Pb-free packaging options.
• XA Automotive version available.
4.1.1.5.3.–ARCHITECTURAL
The architecture of FPGA consists in five fundamental elements.
The first one is the configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus storage elements used
as flip-flops or latches. CLBs perform a wide variety of logical functions
as well as store data. The second is the Input/output Blocks (IOBs)
control the flow of data between the I/O pins and the internal logic of
the device. Each IOB supports bidirectional data flow plus 3-state
operation. Supports a variety of signal standards, including four high-
performance differential standards. Double Data-Rate (DDR) registers
are included. The Block RAM provides data storage in the form of 18-
Kbit dual-port blocks. With the Multiplier Blocks, we could accept two
18-bit binary numbers as inputs and calculate the product. And the
last element is the Digital Clock Manager (DCM) Blocks, this element,
provide self-calibrating, fully digital solutions for distributing, delaying,
multiplying, dividing, and phase-shifting clock signals.
These elements are organized as shown in Figure 2:

Figure 3
The following points, describes more detailed de architecture of
the FPGA. In addition, apart from five fundamentals elements, we also
describe these functions:
• Clocking Infrastructure
• Interconnect
• Configuration
• Powering Spartan-3E FPGA
4.1.1.5.3.1.- INPUT/OUTPUT BLOCKS (IOBS):
The Input/output Block (IOB) provides a programmable,
unidirectional or bidirectional interface between a package pin and
the FPGA’s internal logic. The IOB is similar to that of the Spartan-3
family with the following differences:
• Input-only blocks are added
• Programmable input delays are added to all blocks
• DDR flip-flops can be shared between adjacent IOBs
The unidirectional input-only block has a subset of the full IOB
capabilities. Thus there are no connections or logic for an output path.
The following paragraphs assume that any reference to output
functionality does not apply to the input-only blocks. The number of
input-only blocks varies with device size, but is never more than 25% of
the total IOB count. There are three main signal paths within the IOB:
the output path, input path, and 3-state path.

The input path carries data from the pad, which is bonded to a
package pin, through an optional programmable delay element
directly to the line. After the delay element, there are alternate routes
through a pair of storage elements to the IQ1 and IQ2 lines. The IOB
outputs I, IQ1, and IQ2 lead to the FPGA’s internal logic. The delay
element can be set to ensure a hold time of zero.
The output path, starting with the O1 and O2 lines, carries data
from the FPGA’s internal logic through a multiplexer and then a three-
state driver to the IOB pad. In addition to this direct path, the
multiplexer provides the option to insert a pair of storage elements.
The 3-state path determines when the output driver is high
impedance. The T1 and T2 lines carry data from the FPGA’s internal
logic through a multiplexer to the output driver. In addition to this
direct path, the multiplexer provides the option to insert a pair of
storage elements.
All signal paths entering the IOB, including those associated with
the storage elements, have an inverter option. Any inverter placed on
these paths is automatically absorbed into the IOB.
4.1.1.5.3.2.- CONFIGURABLE LOGIC BLOCKS (CLBS):
The Configurable Logic Blocks (CLBs) constitute the main logic
resource for implementing synchronous as well as combinatorial
circuits. Each CLB contains four slices, and each slice contains two
Look-Up Tables (LUTs) to implement logic and two dedicated storage
elements that can be used as flip-flops or latches. The LUTs can be
used as a 16x1 memory (RAM16) or as a 16-bit shift register (SRL16),
and additional multiplexers and carry logic simplify wide logic and
arithmetic functions. Most general-purpose logic in a design is
automatically mapped to the slice resources in the CLBs. Each CLB is
identical, and the Spartan-3E family CLB structure is identical to that
for the Spartan-3 family. The CLBs are arranged in a regular array of
rows and columns as shown in Figure 3.

Figure 4
All of the CLB comprises four interconnected slices, as shown in
Figure 4. These slices are grouped in pairs. Each pair is organized as a
column with an independent carry chain. The left pair supports both
logic and memory functions and its slices are called SLICEM. The right
pair supports logic only and its slices are called SLICEL. Therefore half
the LUTs support both logic and memory (including both RAM16 and
SRL16 shift registers) while half support logic only, and the two types
alternate throughout the array columns. The SLICEL reduces the size of
the CLB and lowers the cost of the device, and can also provide a
performance advantage over the SLICEM.

Figure 5
4.1.1.5.3.3.- BLOCK RAM:
The devices of the board incorporate 4 to 36 dedicated block
RAMs, which are organized as dual-port configurable 18 Kbit blocks.
Functionally, the block RAM is identical to the Spartan-3 architecture
block RAM. Block RAM synchronously stores large amounts of data
while distributed RAM, previously described, is better suited for
buffering small amounts of data anywhere along signal paths. This
section describes basic block RAM functions.
All of the block RAM is configurable by setting the content’s initial
values, default signal value of the output registers, port aspect ratios,
and write modes. Block RAM can be used in single-port or dual-port
modes.
4.1.1.5.3.4.- DEDICATED MULTIPLAYERS:
Also the devices of the board provide 4 to 36 dedicated multiplier
blocks per device. The multipliers are located together with the block
RAM in one or two columns depending on device density.
4.1.1.5.3.5.- DIGITAL CLOCK MANAGER (DCM):

The DCM provides flexible, complete control over clock frequency,
phase shift and skew. To accomplish this, the DCM employs a Delay-
Locked Loop (DLL), a fully digital control system that uses feedback to
maintain clock signal characteristics with a high degree of precision
despite normal variations in operating temperature and voltage.
The DCM supports three major functions:
• Clock-skew Elimination: Clock skew within a system occurs due
to the different arrival times of a clock signal at different points
on the die, typically caused by the clock signal distribution
network. Clock skew increases setup and hold time
requirements and increases clock-to-out times, all of which are
undesirable in high frequency applications. The DCM eliminates
clock skew by phase-aligning the output clock signal that it
generates with the incoming clock signal. This mechanism
effectively cancels out the clock distribution delays.
• Frequency Synthesis: The DCM can generate a wide range of
different output clock frequencies derived from the incoming
clock signal. This is accomplished by either multiplying and/or
dividing the frequency of the input clock signal by any of
several different factors.
• Phase Shifting: The DCM provides the ability to shift the phase of
all its output clock signals with respect to the input clock signal.
4.1.1.5.3.6.- CLOCKING INFRAESTUCTURE:
The Spartan-3E clocking infrastructure provides a series of low-
capacitance, low-skew interconnect lines well-suited to carrying high-
frequency signals throughout the FPGA. The infrastructure also includes
the clock inputs and BUFGMUX clock buffers/multiplexers. The Xilinx
Place-and-Route (PAR) software automatically routes high-fanout
clock signals using these resources.
BUFGMUX is a synthesis constraint. When one clock signal drives a
group of sequential components, and all these components have the
same clock enable signal, normally a BUFGP element is inferred to
drive all of the clock pins, and an IBUF element is inferred to drive all of
the clock enable pins.

4.1.1.5.3.7.- INTERCONECT:
Is the connection between the inputs and outputs of the elements
inside the FPGA, such IOBs, CLBs, DCMs, and block RAM. There are
four kinds of interconnects: long lines, hex lines, double lines, and
direct lines.
4.1.1.5.3.8.- CONFIGURATION:
The FPGA read their internal configuration from a nonvolatile
memory and this is the memory that keeps the program. The reading
is done on serial form, upon completion of the transfer FPGA is
configured and begins running. This burden is carried out in the power-
up or a reset of the device.
4.1.1.5.3.9.- POWERING SPARTAN-3E FPGA:
There are two supply inputs for internal logic functions, VCCINT and
VCCAUX. Each of the four I/O banks has a separate VCCO supply
input that powers the output buffers within the associated I/O bank.
All of the VCCO connections to a specific I/O bank must be
connected and must connect to the same voltage.
4.1.1.6. - ANALOG DIGITAL CONVERTOR (ADC):
The board has two-channel analog capture circuit, the pre-
amplifier and an analog to digital converter (ADC). Both are serially
programmed and controlled by the FPGA.

Figure 6
The circuit has two pins called VINA and VINB. By this pins the
analog capture circuit, we can acquire the analog voltage and
converts it to a 14-bit digital representation, and D [13:0] .In this project
has been used only the VINA. The equation to obtain this is expressed
by:
The gain, appear in the pre-amplifier and we can see in the table 1
the allowable different values for the gain. The reference voltage for
the amplifier and the ADC is 1.65V and around this value, the ADC has
a maximum range of ±1.25V.
Finally, the ADC presents a 14-bit, two’s complement digital output.
A 14-bit, two’s complement number represents values between -213
and 213-1. Therefore, the quantity is scaled by 8192, or 213.
4.1.1.6.1. - PRE-AMPLIFIER:

The LTC6912-1, that there is at the figure 5, gives to the circuit, two
independent inverting amplifiers with programmable gain. The aim of
the amplifier is to scale the incoming voltage on VINA or VINB so that it
maximizes the conversion range of the DAC, namely 1.65 ± 1.25V.
• Programmable GAIN:
A3 A2 A1 A0 Input voltage rangeGAIN
B3 B2 B1 B0 Minimum Maximum
0 0 0 0 0
-1 0 0 0 1 0.4 2.9
-2 0 0 1 0 1.025 2.275
-5 0 0 1 1 1.4 1.9
-10 0 1 0 0 1.525 1.775
-20 0 1 0 1 1.5875 1.7125
-50 0 1 1 0 1.625 1.675
-100 0 1 1 1 1.6375 1.6625
Table 1
Therefore, in the design of the program, we put a constant gain of -
1. With this gain, the values that we have in the VINA, can be less
limited. Otherwise, we have to be careful to not put a voltage higher
than 2.9.
• Interface:
Interface signals between the FPGA and the amplifier.
Signal FPGA Pin Direction Description
SPI_MOSI T4 FPGA→AD Serial data: Master Output,
Slave Input.
Presents 8-bit programmable
gain settings, as defined in

Table 1.
AMP_CS N7 FPGA→AMP Active-Low chip-select. The
amplifier gain is set when
signal returns High.
SPI_SCK U16 FPGA→AMP Clock
AMP_SHDN P7 FPGA→AMP Active-High shutdown, reset
AMP_DOUT E18 FPGA→AMP Serial data. Echoes previous
amplifier gain settings. Can be
ignored in most applications.
Table 2
• SPI Control Interface:
SPI communications interface with the amplifier is reflected in figure 6.
Figure 7
The AMP_DOUT output from the amplifier, takes previous gain
settings. As show in the figure 7, when the AMP_CS go to the low value
the SPI transaction start. The rising edge of the SPI_SCK gives the order
to SPI_MOSI to capture the serial data of the amplifier. And with the
falling edge of the SPI_SCK, the serial data is send to the AMP_DOUT.

Figure 8
4.1.1.6.2. -ANALOG TO DIGITAL CONVERTER (ADC):
The LTC1407A-1 provides two ADCs.
• Interface:
.
This table show, the interface signals between the FPGA and the
ADC.
Signal FPGA
pin
Direction Description
SPI_SCK U16 FPGA→ADC Clock
AD_CONV P11 FPGA→ADC Active-High shutdown and
reset.
SPI_MISO N10 FPGA→ADC Serial data: Master Input,
Serial Output. Presents the
digital representation of
the sample analog values
as two 14-bit two’s
complement binary values.
Table 3
• SPI Control Interface:

The conversion starts with the rising edge of the AD_CONV. The
maxim sample rate is approximately 1.5 MHz. The ADC present the
digital value as 14-bit, two’s complement binary value.
Figure 9
In the figure 9, is described with more details. Here, SPI_SCK
clock cycles so that the ADC leaves the SPI_MISO signal in the high-
impedance state. Otherwise, the ADC blocks communication to the
other SPI peripherals.
Figure 10

4.1.1.7. - HEADER J2:
By this header, we connect the Xbee to the Spartan-3E. The J2
header is the bottom-most 6-pin connector along the right edge of
the board. As show in the figure 5, the J2 header has four pins connect
to the FPGA, from FX_IO5 to FX_IO8 and also, we can see that the
board supplies 3.3v to the header.
Figure 11
4.1.2. - TEMPERATURE PROBE MODEL EI-1022:
This temperature probe, consist of a semiconductor temperature
sensor, which in turn is mounted, in a plastic tube with current limiting
sensor. The probe should be connected to a 5v DC and for output
give a nominal 3v at room temperature. The probe is suitable for air
and surface applications.
For the electrical connections, the probe has three cables. They
are red, black and white. The first one, the red, is the cable that has to
be connected to +5v DC, the black one is the ground and the white
the output.
Moreover, in our program to transform this output voltage into
°F, °C or °K, we must put the following expressions into our program.

However, our project is design to give the °C; therefore, we only
have to take account of the first.
4.1.2.1. – SPECIFICATIONS:
• Range: -40°C to 100°C (-40°F to 212°F)
• Output: 10 mV per °K absolute
• Sensor device in probe: LM335A
• Cable length: 6 ft supplied, 500 ft user extended
• Probe dimensions: 4 in x 0.25 diameter
• Power: +5 VDC at .001 Amp
• Output Load: 50K or greater or 100 uA max
• Accuracy:
1. +/- 1°C Typical Room Temperature
2. +/- 3°C Max Room Temperature
3. +/- 2°C Typical -40°C to 100°C
4. +/- 5°C Max -40°C to 100°C
4.1.3. -XBEE:
The Xbee are some modules that are engineered to operate
with ZigBee protocol and with this, we can have wireless connection.
ZigBee networks are called personal area networks (PAN). The
modules require minimal power and provide reliable delivery of data
between remote devices. The connection to the board is given
through the header J2, but the assembly will be explained at a later
point.
4.1.3.1.-FEATURES:
• Indoor/Urban: up to 300’ (100 m)

• Outdoor line-of-sight: up to 1 mile (1.6 km)
• Transmit Power Output: 100 mW (20 dBm) EIRP
• Receiver Sensitivity: -102 dBmRF Data Rate: 250,000 bps
• TX Current: 295 mA (3.3 V)
• RX Current: 45 mA (3.3 V)
• Power-down Current: < 1 μA 25°C
4.1.3.2.- SPECIFICATIONS:
Specification XBee ZNet 2.5
Performance
Indoor/Urban Range up to 133 ft. (40 m)
Outdoor RF line-of-sight Range up to 400 ft. (120 m)
Transmit Power Output 2mW (+3dBm), boost mode
enabled 1.25mW (+1dBm), boost
mode disabled
RF Data Rate 250,000 bps
Serial Interface Data Rate
(software selectable)
1200 - 230400 bps (non-standard
baud rates also supported
Receiver Sensitivity -96 dBm, boost mode enabled
-95 dBm, boost mode disabled
Power Requirements
Supply Voltage 2.1 - 3.6 V
Operating Current (Transmit,
max output power)
40mA ( 3.3 V, boost mode
enabled) 35mA (@ 3.3 V, boost
mode disabled)
Operating Current (Receive)) 40mA ( 3.3 V, boost mode
enabled) 38mA (@ 3.3 V, boost
mode disabled)
Idle Current (Receiver off) 15mA
Power-down Current < 1 uA 25oC
General
Operating Frequency Band ISM 2.4 GHz
Dimensions 0.960” x 1.087” (2.438cm x
2.761cm)
Operating Temperature -40 to 85º C (industrial)
Antenna Options Integrated Whip, Chip, RPSMA,
or U.FL Connector*
Networking & Security
Supported Network Topologies Point-to-point, Point-to-

multipoint, Peer-to-peer, and
Mesh
Number of Channels 16 Direct Sequence Channels
Addressing Options PAN ID and Addresses, Cluster
IDs and Endpoints (optional)
Table 4
4.1.3.3.- PIN SIGNALS:
The minimum connection is connecting, VCC, GND, DOUT &
DIN. The following table shows the pin assignment for the Xbee.
And to support serial firmware upgrades: VCC, GND, DIN, DOUT,
RTS & DTR. In our project will be used VCC, GND and DIN the others
are not necessary.
Pin
#
Name Direction Description
1 Vcc Power supply
2 DOUT Output UART Data Out
3 DIN / CONFIG Input UART Data In
4 DIO12 Either Digital I/O 12
5 RESET Input Module Reset (reset pulse
must be at least 200 ns)
6 PWM0 / RSSI /
DIO10
Either PWM Output 0 / RX Signal
Strength Indicator / Digital IO
7 PWM / DIO11 Either Digital I/O 11
8 [reserved] Do not connect
9 DTR / SLEEP_RQ/
DIO8
Either Pin Sleep Control Line or
Digital IO 8
10 GND Ground
11 DIO4 Either Digital I/O 4
12 CTS / DIO7 Either Clear-to-Send Flow Control or
Digital I/O 7
13 ON / SLEEP / DIO9 Output Module Status Indicator or
Digital I/O 9
14 [reserved] Do not connect
15 Associate / DIO5 Either Associated Indicator, Digital
I/O 5
16 RTS / DIO6 Either Request-to-Send Flow Control,
Digital I/O 6

17 AD3 / DIO3 Either Analog Input 3 or Digital I/O 3
20 AD0 / DIO0 /
Commissioning
Button
Either Analog Input 0, Digital IO 0, or
Commissioning Button
Table 5
Figure 12
4.1.3.4. -OPERATION:

The Xbee modules interface to a host device through a logic-
level asynchronous serial port. As show in the figure 12, the pins of the
module can be connected directly to the board, taking into account
the maximum VCC.
Figure 13
Data enters the module UART through the DIN (pin 3) as an
asynchronous serial signal. The signal should idle high when no data is
being transmitted. This is formed, by one start bit (low), 8 data bits
(least significant bit first) and a stop bit (high).
When the module is not transmitting or receiving, the module is
on idle mode. Therefore, when the module is ready for transmit or
receive the data, the module exit the idle mode and attempt to
transmit the data into the transmit mode. Before this, the module, the
module ensures that a 16-bit network address and route to the
destination node have been established. If a module with a matching
network address is not discovered, the packet is discarded. When
data is transmitted, a network-level acknowledgement is transmitted
back. This acknowledgement packet indicates to the source node
that the data packet was received by the destination node. If this is
not received, the module re-transmit the data until is all transmitted.
The transmission finish when the other module transmits a RF valid
packet. To modify or read RF Module parameters, the module must
first enter into command mode but we are not going to deepen more
in this.

To transmit the data, the program must be configured
according the following points.
1. No character send for one second
2. Input three plus characters (+++)
3. character send for one second
After transmit this, the modules are ready to send the data from
one module to another.
One the other hand, we have the ZigBee protocol. Zigbee
networks are called personal area networks (PAN). Each network
contains a 16-bit identifier called a PAN ID. This protocol defines three
device types: coordinator, router and end device.
Regarding the coordinator, is the responsible for selecting the
channel and PAN ID. Once it has started a PAN, the coordinator can
allow routers and end devices to join the PAN. A router must join a
ZigBee PAN before it can operate. After joining a PAN, the router can
allow other routers and end devices to join the PAN. The purpose of
the end device is similar than the route, to join a ZigBee PAN. The end
device, however, cannot allow other devices to join the PAN, nor can
it assist in routing data through the network. An end device can
transmit or receive RF data transmissions. End devices are intended to
be battery powered devices. Since the end device may sleep, the
router or coordinator that allows the end device to join must collect all
data packets intended for the end device, and buffer them until the
end device wakes and is able to receive them.
Therefore, ZigBee networks are formed when a coordinator first
selects a channel and PAN ID. Then, the router and the end device
can join a ZigBee PAN. The PAN ID is selected by the coordinator and
the other become part of the PAN when they join a PAN.
Regarding the communication of the ZigBee, this supports
device addressing and application layer addressing. Device
addressing specifies the destination address of the device a packet is
destined to. The other one, the application layer addressing indicates

a particular application recipient, known as a Zigbee endpoint, along
with a message type field called a Cluster ID.
4.1.4. –LABVIEW:
LabVIEW (Laboratory Virtual Instrument Engineering Workbench)
is a graphical programming language that uses icons instead of lines
of text to create applications. In contrast to text-based programming
languages, like VHDL, C++ or JAVA, in which you design your program
with an especial language or text, in Labview, the program is design in
the block diagram with nodes and this determines the execution order
of the VIs or function. VIs, or virtual instruments, is LabVIEW programs
that imitate physical instruments. The graphical language is named "G"
and the block diagram contains this code. It is specially designed to
take measurements, analyze data, and present results to the user.
In LabVIEW, you build a user interface by using a set of tools and
objects. There are two panels, the front panel for the user and the
block panel. A VI contains the following three components:
• Front panel: Serves as the user interface. You build the front
panel using controls and indicators, which are the interactive
input and output terminals of the VI, respectively. The figure 13 is
an example of a front panel.
Figure 14
• Block diagram: The block diagram contains this graphical
source code, also known as G code or block diagram code.

Front panel objects appear as terminals on the block diagram.
At this panel, you have different terminals, nodes, structures, and
all this may be related by wires. The figure 14 is an example.
Figure 15
• Icon and connector pane—identifies the interface to the VI so
that you can use the VI in another VI. A VI within another VI is
called a subVI. A subVI corresponds to a subroutine in text-
based programming languages.
4.1.4.1. – DATAFLOW PROGRAMMING:
The programming language used in LabVIEW, called G, is a
dataflow programming language. The execution is determined by the
structure of a graphical block diagram on which the programmer
connects different function-nodes by drawing wires. These wires
propagate variables and any node can execute as soon as all its
input data become available and G is also inherently capable of
parallel execution. The programmers who use conventional
programming often show certain reluctance to start using the Labview
dataflow scheme. The reason they give is prone to race conditions.
That isn’t a good reason for abandon Labview because the dataflow
(which can be forced, typically by linking inputs and outputs of nodes)
completely defines the execution sequence, and that can be fully

controlled by the programmer. Thus, the execution sequence of the
LabVIEW graphical syntax is as well-defined as with any textually
coded language such as C, Visual BASIC, Python, etc. Furthermore,
LabVIEW does not require type definition of the variables; the wire
type is defined by the data-supplying node.
4.1.4.2. – GRAPHICAL PROGRAMMING:
LabVIEW programs are called virtual instruments (VIs). A virtual
instrument can either be run as a program, with the front panel serving
as a user interface, or, when dropped as a node onto the block
diagram, the front panel defines the inputs and outputs for the given
node through the connector pane. This implies each VI can be easily
tested before being embedded as a subroutine into a larger program.
For complex algorithms or large-scale code it is important that the
programmer possess an extensive knowledge of the special LabVIEW
syntax and the topology of its memory management.
4.1.4.3. – BENEFITS:
One benefit of LabVIEW over other development environments
is the extensive support for accessing instrumentation hardware.
Drivers of many different types of instruments and buses are included
or are available for inclusion. These present themselves as graphical
nodes. So, people with limited coding experience can write programs
and deploy test solutions in a reduced time frame when compared to
more conventional or competing systems.
Although, another benefit is the new hardware driver topology
(DAQmxBase), which consists mainly of G-coded components with
only a few register calls through NI. The DAQmxBase driver is available
for LabVIEW on Windows, Mac OS X and Linux platforms.
Many libraries with a large number of functions for data
acquisition, signal generation, mathematics, statistics, signal
conditioning, analysis, etc., along with numerous graphical interface

elements are provided in several LabVIEW package options. In
addition, LabVIEW includes a text-based programming component
called MathScript with additional functionality for signal processing,
analysis and mathematics. MathScript can be integrated with
graphical programming using "script nodes" and uses .m file script
syntax that is generally compatible with Matlab (Matlab is another
program, for the design and control of transfer functions…).The
LabVIEW Professional Development System allows creating stand-
alone executables and the resultant executable can be distributed an
unlimited number of times. The run-time engine and its libraries can be
provided freely along with the executable.
A benefit of the LabVIEW environment is the platform
independent nature of the G code, which is (with the exception of a
few platform-specific functions) portable between the different
LabVIEW systems for different operating systems (Windows, Mac OS X
and Linux).
There is a low cost LabVIEW Student Edition aimed at
educational institutions for learning purposes. There is also an active
community of LabVIEW users who communicate through several e-
mail groups and Internet forums
4.1.4.4. - CRITICISM:
LabVIEW is a proprietary product of National Instruments. Unlike
common programming languages such as C or FORTRAN, LabVIEW is
not managed or specified by a third party standards committee such
as ANSI.
Building a stand-alone application with LabVIEW requires the
Application Builder component which is included with the Professional
Development System but requires a separate purchase if using the
Base Package or Full Development System. Compiled executables
produced by the Application Builder are not truly standalone in that
they also require that the LabVIEW run-time engine be installed on any
target computer on which users run the application. The use of

standard controls requires a runtime library for any language and all
major operating system suppliers supply the required libraries for
common languages such as 'C'. However, the runtime required for
LabVIEW is not supplied with any operating system and is required to
be specifically installed by the administrator or user. This requirement
can cause problems if an application is distributed to a user who may
be prepared to run the application but does not have the inclination
or permission to install additional files on the host system prior to
running the executable.
There is some debate as to whether LabVIEW is really a general
purpose programming language (or in some cases whether it is really
a programming language at all) as opposed to an application-
specific development environment for measurement and automation.
4.1.5.- EI-1022 INTERFACE TO THE BOARD:
Like previously we have mentioned, we cannot put a voltage
higher than 3v to the ADC. Therefore, it is necessary to reduce the
voltage without lose sensibility of the temperature probe. To make this
possible, we create an electronic circuit composed with different
devices, as show in the figure 16.

Figure 16
The source of the circuit is 5 volts, and in our project, the source
that we used is take it from the LCD of the Spartan-3E. The RT
corresponds to the temperature probe that has an output of 3 volts.
Therefore, to be used with the ADC, we must reduce this voltage. The
output reference normally is of 3 volts as we can see in the section
4.1.2. For that reason, we have the Ra tension divisor with an output of
3 volts and the Rb tension divisor dividing this tension and giving 1.52
volts. These voltages are our reference and to the Rb, we must add
the difference between Rt and Ra. Thus, when the voltage of the
temperature probes change, we can add it the difference to our
input ADC.
For example, imaging that the output of the temperature probe
is of 3.3 volts. With the first op-amp we can get the difference
between this voltage and 3 volts. And with the second op-amp add it
to our reference of 1.52 volts. Thus, we can reduce the error. We use
two LM358 operational amplifiers because there amplifiers can work
with a single power supply of 5 volts and like this, we don`t need any

external source, we can use the LCD source as we explained it before.
We can see the circuit of the first one at the figure 17 and the circuit of
the second op-amp at the figure 18.
Figure 17
I1=I2 I3=I4
We can reduce this expression if we consider that the R3 and R1
in parallel are the same to the R2 and R4.

Therefore, with this circuit we get de difference between the
two voltages and if the R3 is between 0 and infinite we can get a gain
of 1.
Figure 18
I1=I2 I3=I4
We can reduce this expression if we consider that the R2 and R1
in parallel are the same to the R3 and R4.

For the resistors that have one point in common, we use one
tension divisor as we can see in the assembly section.
4.1.5.1.- LM358 OPERATIONAL AMPLIFIER:
The LM158 series consists of two independent, high gain, internally
frequency compensated operational amplifiers which were designed
specifically to operate from a single power supply over a wide range of
voltages. Operation from split power supplies is also possible and the low
power supply current drain is independent of the magnitude of the power
supply voltage.
Application areas include transducer amplifiers, dc gain blocks and all
the conventional op amp circuits which now can be more easily
implemented in single power supply systems. For example, the LM158 series
can be directly operated off of the standard +5V power supply voltage
which is used in digital systems and will easily provide the required interface
electronics without requiring the additional ±15V power supplies.
4.1.5.1.1.-ADVANTAGES:
• Two internally compensated op amps
• Eliminates need for dual supplies
• Allows direct sensing near GND and VOUT also goes to GND
• Compatible with all forms of logic
• Power drain suitable for battery operation
•
4.1.5.1.2.-FEATURES:
• Available in 8-Bump micro SMD chip sized package.
• Internally frequency compensated for unity gain
• Large dc voltage gain: 100 dB
• Wide bandwidth (unity gain): 1 MHz
• (temperature compensated)
• Wide power supply range:
— Single supply: 3V to 32V

— or dual supplies: ±1.5V to ±16V
• Very low supply current drain (500 μA)—essentially
• independent of supply voltage
• Low input offset voltage: 2 mV
• Input common-mode voltage range includes ground
• Differential input voltage range equal to the power
• supply voltage
• Large output voltage swing
4.1.5.1.3.- CONNECTION DIAGRAM:
Figure 19

4.2. – OPERATIVE PROCEDURE:
4.2.1. – LEARNING LABVIEW:
For a better understand of our project, is necessary, to learn how
to use the LabView environment. There are many tutorials and
different books, for learn the operation of the program from a
beginner level. One of the tutorials that we used is the learning
labview in 6 hours. At the web page of national instruments is possible
to found some other tutorials and exercises for learn how to use the
program. Here also, is possible to found forums to do any type of
punctual questions about LabView. All this helped us to acquire
necessary knowledge about how to use LabView’s components and
functions to build our program.
4.2.2.- PROGRAM DESCRIPTION:
This project is divided in two big parts, the first one is the Analog
to Digital Conversion and the second part is formed for different
subVIs. This subVIs are formed part of the transformation of data
acquired during the first part, for later send the data through Xbee to
another computer.
4.2.3. – CREATING A FPGA PROJECT:
The requirements and the application notes need it:
• LabVIEW 8.5 and LabVIEW FPGA Module 8.5.
• Software is not supported on 64-bit Windows Vista.
• If you already have Xilinx tools installed and your Spartan-3E is
plugged in, Windows will not allow you to install the Xilinx USB
cable driver. You can either turn off your Spartan-3E during
install or uninstall the USB cable in the Windows Device
Manager.

When the software is installed, you have to connect the USB B
Connector from the USB cable provided to the Spartan-3E Starter
board as show in the figure 15 and connect the USB A Connector from
the USB cable to the host computer. Later, connect the power cable
provided to the Spartan-3E Starter Board power port. Switch the
On/Off Dip Switch to On to power on the Spartan-3E Starter board.
When the power is turned on to the device, the Power LED located at
the top-left corner of the device will light up.
Figure 20
The following points describe how can create a Spartan-3E
target:
1. Open LabVIEW 8.5. To create an empty project; click Empty
Project on the Getting Started window or go to File »New
Project.
2. Right-click My Computer under the project name and go to
New »Targets and Devices as shown in Figure 16.

Figure 21
3. With the Add Targets and Devices dialog box open, select the
new target or device radio button. Under Targets and Devices,
expand Xilinx University Program and select the Spartan-3E
Starter Board as the target.
4. Your new project should now contain the Spartan-3E Starter
Board as a target. To create an FPGA VI, right-click the name
FPGA target (Dev1, Spartan-3E Starter Board) and select
New»VI. Note that your new VI is under the FPGA tree. This
indicates that the VI belongs to the FPGA target and not the
host computer. This VI will be compiled to VHDL code and then
downloaded via USB to the Spartan-3E target.
After this, is also necessary to put the FPGA I/O that we will use.
For that, again we put the steps. LabVIEW FPGA has implemented some
powerful tools which are created in the Project Explorer window.
These tools include creation of:
- FPGA I/O Resources
- FPGA FIFOs
- Derived Clocks
1. In the LabVIEW Project Explorer, we can create I/O nodes for
any FPGA target already configured in our project. Create a
new I/O item by right clicking on the FPGA target and going to
New>>FPGA I/O.

Figure 22
2. Expand the devices that are going to use in the program
clicking first in the device and later to add. In this project used
are:
• DAC: DAC_CS
• ADC: AD_CONV, AMP_SHDN, AMP_DOUT
• StrataFlash: SF_CEO, SF_WE, SF_OE
• SPI/STMicro Serial Flash: SPE_MOSI, SPI_MISO, SPI_SCK,
SPI_SS_B
• FPGA Configuration: FPGA_INT_B
• Expansion Connectors: FX2_IO8_J2_3

Figure 23
3. Should be something like figure 19.
Figure 24
4.2.4. – PROGRAM DEVELOPMENT:
At this point, we are going to try to explain step by step the
development of the program. As mentioned earlier, the program of
this project has two parts, so first we are going to explain the Analog
Digital Conversion.
4.2.4.1. - ANALOG TO DIGITAL:

The first part, in our project is called Project Program, and
around this the program is design. The figure 20 and 21 show this part.
The whole program is wrapped with a while loop that never ends, like
that our program is always sending our value automatically. The next
structure is a case structure. The case selector is wire to a control start
reading control and if this is not true the program does not start. This
control appears at the front panel for a good use of the user. The next
structure is again a while loop, in this case, the loop repeats every
1000ms. With this, what we do is a reading every 1000ms.
The ADC is design with a flat sequence structure. In the first
frame we have the subVI Preamplifier, wired with a constant value of
17, but we are going to explain later the reason of this choose. In the
second frame, we disable other devices. The SPI bus signals are shared
by other devices on the board. It is vital that other devices are
disabled when the FPGA communicates with the DAC to avoid bus
contention. Table 6 provides the signals and logic values required to
disable the other devices. Although the StrataFlash PROM is a parallel
device, its least-significant data bit is shared with the SPI_MISO signal.
Signal Disabled Device Disable Value
SPI_SS_B SPI serial Flash 1
AMP_CS Programmable pre-
amplifier
1
AD_CONV Analog-to-Digital
Converter (ADC)
0
SF_CE0 StrataFlash Parallel
Flash PROM
1
FPGA_INIT_B FPGA_INIT_B Platform
Flash PROM
1
Table 6
Later, we initialize the conversion putting down the clock
SPI_SCK and the AD_CONV. The explanation of the reason for this
design is more detailed in the section 4.1.1.6.- Analog to Digital
Convertor.

Figure 25

Figure 26
Therefore, at the end of this part, we have a digital number of 14
bits. But as we see in the expression of section 4.1.1.6, sometimes, VIN is
bigger than 1.65 but another times is lower. So the final value can be
positive or negative. As we see in the section 4.1.1.6 in the conversion,
we get the second complement of original. Thus, sometimes the
digital number is not the value that we need. To resolve this we create
one subVI that treat this value, the name of this is subVI 2.complement.
Thus, in the next point we are going to explain this problem and what
is the subVI do, for resolve it.

4.2.4.2. –TREATING THE DIGITAL VALUE:
The second part of the program, begin with this subVI and the
aspect of this part is show in figure 22.
Figure 27
By the foregoing mentioned, now we have a digital value of
14bit. This value is in the second complement of the binary numbers.
So, if the final number is negative there is not problem but if is positive
the digital value is wrong (remember the GAIN).
We are going to explain this with two examples:
1. Imaging that our input is of 1.2v, by this expression:
•
• D = 2949.12 or Ex= 0B85 (hexadecimal)
• At binary the number is 0000 1011 1000 0101.
• Doing the first complement: 1111 0100 0111 1010
• Second complement:
1111 0100 0111 1010
+ 1

1111 0100 0111 1011
• Hexadecimal = F47B
• And the program gives for the input or 1.2 volts 3.7197 or a
hexadecimal value of CB04, into binary: 1100 1011 0000
0100.
2. Now imaging a value of 1.8 volts.
• D = -983.04 Ex = 03D7
• At binary the number is 0000 1000 1111 0101
• At the second complement: 1111 1100 0010 1001 or Ex =
FC39 and this is the value that we need.
Therefore, we can deduct that when the value is positive the
binary number that we want is not the one that we want. But if we
compare the two binary numbers:
0000 1011 1000 0101
1100 1011 0000 0100
We can see that the biggest difference is at the two most
important bits, 15 and 14. Therefore, the objective of this subVI is to
delete these two bits. For that, we must know the voltage limits for the
ADC. As we see with the GAIN = -1 the voltage must be between 0.4
and 2.9.
At our expression, with a value of 0.4v we get D=8192 and with
the value of 2.9 we get D=-8192. In the figure 22 we can see that we
limit the value between -8192 and 8192, as we explained before. In this
case is true so we take the decimal value of this binary number
directly.

Figure 28
When the binary value is wrong, this is not between the limits, so
the case is false. At the figure 23, we can see that in the false case,
the bits 15 and 14 put it at false. With this, binary number is more similar
to the correct one. After, we convert the binary number to decimal,
using a Boolean array to number and another device, to word integer.
Figure 29

4.2.4.3.- OBTAIN THE TEMPERATURE:
As we already mentioned at section 4.1.2 to calculate the value
of the temperature, we have to apply one expression. Therefore, this
subVI have this expression, as we can see in the following figure. Thus,
in this subVI we have the two expressions.
However, at FPGA project we can’t use normal arithmetic
procedures; therefore we must use Fixed Point. Fixed point is a format
for representing numbers on digital processing devices. It is a data
type used by a programming language or hardware descriptive
language (HDL) to determine how to interpret bits in a memory
location. If the fixed-point data type has an inferior range and
precision compared to floating point, why use fixed-point numbers?
The most common reason is because the selected processing platform
does not support floating-point arithmetic or cannot process floating-
point numbers efficiently. FPGA is one good example. While it is
possible to implement floating-point processing on an FPGA, it is not
speed-efficient and can significantly limit the amount of logic that you
can place on the FPGA.
From the web page of National Instruments, is necessary to
download the fixed point file and install it with our program. Here also,
is possible to found many tutorials and information about the using of
the fixed points.

Figure 30
The following equations are used in the subVI.
1.
2.
4.2.4.4. – STARTING THE CONVERSION TO ASCII:

In the figure 26, show the initial process to send the temperature
value by the Xbee. The purpose of this subVI is to separate the value
into two numbers. Thus, later we can manipulate the value and
convert it into ascii.
For example, if we get a value of 25 degrees, this subVI separate
this number. On the one hand, we get the number 2 and on the other
hand, the value 5. This is possible, dividing the value by 10 and into the
properties of the FXP if we put it for no get decimal values; like that we
get the number 2. Later to get the number 5, we subtract the number
25 with 20.
Figure 31

After this, is necessary to convert the number into ascii. Thus, the
figure 27, shows the block diagram of this subVI. For that conversion,
we create a case structure with all the numbers into ascii. And for
example if our number is 2 the output of the case structure we get this
number into ASCII. Therefore, in this structure, are 10 different cases, 0
to 9. The figure 28, is possible to see the ascii table. In our program, we
need two of this subVI, one for each number.
Figure 32

Figure 33
The last part of our program, maybe is the most complicate. The
reason is that we use a loop in this subVI and like this, is difficult to synchronize
it. This subVI is composed in two parts, and the first one, corresponds to the
figure 29. As we can see, the number comes at ASCII form, and the
first thing that we do is to divide into different bits for better shipping. In
our design, we used a flat sequence structure and in each frame we
put a command or data. For example the first frames are design for
start the communication with the Xbee. As we explained before, we
have to send +++, with a delay of one second before and after send
the +++. For send it, we create another subVI that we are going to
explain it later, we can see it in the figure 30. Here, we receive the
data and we send this data bit by bit. For that, there are 7 controls in
this subVI and each control has a local variable. We use these
variables in the frames that we are send it a command or data. For
example in the figure 29 we can see, in the frame number 3, sending
the + command.
Every time that we send a data, it is necessary to maintain the
sequence some time, at least, we now that the data is send it. For this,

after each send, we create a loop with a stop control, and with a
local variable of this stop inside the second frame of the second part,
we wait until the command is send. As show in figure 30.
Figure 34
Figure 35

This part of the subVI is synchronise with the other one using
another flat sequence structure, as show in the figure. The subVI is
inside a case structure, and with this we can control when we want
that our data is send. So after we put our data into a frame, we need
to use another frame to say when we want to send. We can see an
example in the figure 31. We can do this, using again, different local
variables of a control, that in this case, the control in connected to the
case selector. Thus, after the program doesn’t finish with the
command, the program doesn’t continue with the sequence
structure, and like we have explained before, the stop bit is not put it
into false position.
After we send the +++, we send the command to create a new
page. Like this, we always have the temperature value in the first
position of the page of the hyperterminal.
The different command that we have used are possible to found
it in the figure 28.
• + : 00101011
• New page: 00001100
• Space: 0010000
• ° (from figure 32): 11111000
• C: 01000011
At the end, of the first part of the sequence structure, we put the stop
2 in true position to stop the loop and the data send. With this, we can
create a perfect synch. The local variable of this control, is also in the little
sequence structure.

Figure 36
Figure 37
The last part, is the serial communication by the header J2. For
do this possible, first, we have to choose the bps. In our program we
choose the 9600 bps with two stop bits. Thus, is necessary, to coupling

this inside our program, so for send one bit we have to calculate the
delay. We used the FPGA I/O FX2_IO8_J2_3.
Figure 38
Figure 39
4.2.4.5. – PREAMPLIFIER:

The specifications of this are more detailed in section 4.1.1.6.1.
Figure 40
The Serial Peripheral Interface (SPI) is formally described as being a full-
duplex, synchronous, character-oriented channel employing a 4-wire
interface. As each bit is transmitted by the master, the slave also transmits a
bit allowing one byte to be passed in each direction at the same time. In this
case the Spartan-3E is the master and the SPI Amplifier is the slave.
Looking specifically at the LTC6912-1 Amplifier, each communication
is formed of 1 byte or 8-bits. Inside the Amplifier, the SPI interface is formed by
an 8-bit shift register. As a new 8-bit command byte is transmitted to it, the
byte previously sent is echoed back to the master. In order to use the
amplifier this response can be ignored, however, it is a useful to confirm
correct communication is taking place and it is read back.
The amplifier needs to transmit each byte most significant bit
first. So
bit 7 is transmitted and received first and bit 0 is transmitted and
received last. For this, we used a reverse 1D array. As we see, we put
the 17 number like input, the reason is, that with that number, we can
control the gains of VINA and VINB (show table ).
For example:
Sending 17 = 00010001

With this value, the gain of VINA is the -1 and VINB, as we show
in the figure 6. Also will be enough if we put the value of 1 in our
program (1= 00000001). In this case, we only enable the VINA, but as
we see it, is all we need.

V.-ASSEMBLY
Here we are going to make a description with some pictures
about the assembly. The figure 41 is the general vision of our project.
Figure 41
As show in the figure, we can see the temperature probe
connect it to the Spartan-3E using the aforementioned circuit. In the
figure 42, we can see how we get the source from the LCD to be used
for the power of the probe and the circuit and also the ADC
connection. Also at the figure 43, is possible to see the circuit more
detailed and the figure 44 and 45 corresponds to the Xbees
connections from our FPGA to the computer. We can see the result of
this communication in the figure 46.

Figure 42
Figure 43

Figure 44
Figure 45

Figure 46

VI.- FUTURE DEVELOPMENT
There are some different possibilities for do in the future. It would
be a good idea to create a PCB (Printed Circuit Board), to make the
connection between the temperature probe and the board, with the
same purpose than our circuit.
Also, the precision of the measure can increase putting one
different operational amplifier with other characteristics and also
reduce the delay. Would be interesting to use the LCD to reflect the
value of temperature and also make some changes in the program to
give the possibility the user, to select between Celsius, Kelvin....

VII.-REFERENCES
• VHDL:
1. Introductory VHDL From Simulation to Synthesis
Sudhakar Yalamanchili
Xilinx design series
2. http://www.ehu.es/Electronica_EUITI/vhdl/pagina/inici
o.htm
3. http://svenand.blogdrive.com/archive/40.html
• LabView:
1. http://en.wikipedia.org
2. www.ni.com
(i) http://zone.ni.com/devzone/cda/tut/p/id/6930
(ii) http://decibel.ni.com/content/docs/DOC-1407
(iii)http://zone.ni.com/devzone/cda/tut/p/id/4799
(iv)http://www.ni.com/academic/lv_training/how_lear
n_lv.htm
3. http://perso.wanadoo.es/jovilve/tutoriales.html
4. http://www.slideshare.net/fpgabe/labview-fpga
• FPGA:
1. http://www.xilinx.com/
(i) http://www.xilinx.com/support/documentation/spar
tan-3e.htm
3. www.ni.com
• XBEE:
1. http://www.digi.com
• Temperature Probe MODEL EI-1022:
1. http://www.egmont.com.pl/labjack/katalog/ei1022.p
df
• LM358 operational amplifier:
1. http://www.national.com/ds/LM/LM158.pdf

VIII.-ANNEX I
As we have said the language of FPGA VHDL, therefore we do
here a short summary.
VHDL is an acronym for Very high speed integrated circuit
(VHSIC) Hardware Description Language which is a programming
language that describes a logic circuit by function, data flow
behavior, and/or structure. This hardware description is used to
configure a programmable logic device (PLD), such as a field
programmable gate array (FPGA), with a custom logic design. The
general format of a VHDL program is built around the concept of
BLOCKS which are the basic building units of a VHDL design. Within
these design blocks a logic circuit of function can be easily described.
A VHDL design begins with an ENTITY block that describes the
interface for the design. The interface defines the input and output
l1ogic signals of the circuit being designed. The ARCHITECTURE block
describes the internal operation of the design. Within these blocks are
numerous other functional blocks used to build the design elements of
the logic circuit being created.
After the design is created, it can be simulated and synthesized
to check its logical operation. SIMULATION is a bare bones type of test
to see if the basic logic works according to design and concept.
SYNTHESIS allows timing factors and other influences of actual field
programmable gate array (FPGA) devices to effect the simulation
thereby doing a more thorough type of check before the design is
committed to the FPGA or similar device.
Data types:
There are two data types used for defining interfacing and
interconnecting signals - bits and bit_vectors. The bit type defines a
single binary bit type of signal like RESET or ENABLE. It is used anytime
you need to define a single control or data line. For multiple bus
signals, such as data or address buses, an array called a bit_vector is
used. Bit_vectors require a range of bits to be defined and has the
syntax: bit_vector(range). The range for a bit_vector is defined from
the least significant bit (LSB) to the most significant bit (MSB) and can
be set to go from one to the other in ascending or descending order

by using: LSB to MSB or MSB downto LSB. Here are some examples of
bit_vector forms:
- addressbus(0 to 7)
- databus(15 downto 0)
The boolean type has only two values: TRUE (1) and FALSE (0)
and is usually used to hold the results of a comparison or the basis for
conditional statement results.
Number types that are usable in VHDL code are INTEGERS and
REALS. Integers are signed numbers and reals are used for floating
point values. The range of values for both number types is somewhat
dependent on the software application being used.
VHDL provides a method to create a version of an existing type
with a specified range of values by using the SUBTYPE declaration. A
typical example of the use and syntax of this operation is: subtype
SHORTINT is integer range 0 to 255; which creates an integer type,
SHORTINT with a specified range of values from 0 to 255. This is NOT a
new or enumerated (user) type which we shall describe next, but
rather a modified existing type.
ENTITY BLOCK
An entity block is the beginning building block of a VHDL design.
Each design has only one entity block which describes the interface
signals in to a nd out of the design unit. The syntax for an entity
declaration is:
entity entity_name is
port (signal_name,signal_name : mode type;
signal_name,signal_name : mode type);
end entity_name;
An entity block starts with the reserve word entity followed by
the entity_name. Names and identifiers can contain letters, numbers,
and the under score character, but must begin with an alpha
character. Next is the reserved word is and then the port declarations.
The indenting shown in the entity block syntax, is used for
documentation purposes only and is not required since VHDL is
insensitive to white spaces.

A single PORT declaration is used to declare the interface signals
for the entity and to assign MODE and data TYPE to them. If more than
one signal of the same type is declared, each identifier name is
separated by a comma. Identifiers are followed by a colon (:), mode
and data type selections.
In general, there are five types of modes, but only three are
frequently used. These three will be addressed here. They are in, out,
and inout setting the signal flow direction for the ports as input, output,
or bidirectional. Signal declarations of different mode or type are listed
individually and separated by semicolons (;). The last signal
declaration in a port statement and the port statement itself are
terminated by a semicolon on the outside of the port's closing
parenthesis.
The entity declaration is completed by using an end operator
and the entity_name. Optionally, you can also use an end entity
statement. Here is an example of an entity declaration for a set/reset
(SR) latch:
entity latch is
port (s,r : in std_logic;
q,nq : out std_logic);
end latch;
ARCHITECTURE BLOCK
The architecture block defines how the entity operates. This may
be described in many ways, two of which are most prevalent:
STRUCTURE and DATA FLOW or BEHAVIOR formats. The BEHAVIOR
approach describes the actual logic behavior of the circuit. This is
generally in the form of a Boolean expression or process. The
STRUCTURE approach defines how the entity is structured - what logic
devices make up the circuit or design. The general syntax for the
architecture block is:
architecture arch_name of entity_name is
declarations;
begin
statements defining operation;
end arch_name;

1. library ieee;
2. use ieee.std_logic_1164.all;
3. --
4. -- entity block
5. --
6. entity latch is
7. --
8. -- interface signal declarations
9. --
10. port (s,r : in std_logic;
11. q,nq : out std_logic);
12. end latch;
13. --
14. -- architecture block
15. --
16. architecture flipflop of latch is
17. begin
18. --
19. -- assignment statements
20. --
21. q <= r nor nq;
22. nq <= s nor q;
23. end flipflop;
The first two lines imports the IEEE standard logic library
std_logic_1164 which contains predefined logic functions and data
types such as std_logic and std_logic_vector. The use statement
determines which portions of a library file to use. In this example we
are selecting all of the items in the 1164 library. The next block is the
entity block which declares the latch's interface inputs, r and s and
outputs q and nq. This is followed by the architecture block which
begins by identifying itself with the name flipflop as a description of
entity latch.
Within the architecture block's body (designated by the begin
reserved word) are two assignment statements. Signal assignment
statements follow the general syntax of: signal_identifier_name <=
expression; The <= symbol is the assignment operator for assigning a
value to a signal. This differs from the := assignment operator used to
assign an initial literal value to generic identifier used earlier.

A bit_vector or std_logic_vector type is an array of bits. The range
designates the size of the array and the index values to be used by the
array. Elements of the array are accessed by using the array name
and an index value in the form of: array_name(index). The best way to
see how values are assigned to an array is to do an example. This is a
multiplexor entity:
1. library ieee;
2. use ieee.std_logic_1164.all;
3. entity demux is
4. port ( e : in std_logic_vector (3 downto 0);
5. s : in std_logic_vector (1 downto 0);
6. d : out std_logic_vector (3 downto 0));
7. end demux;
8. architecture rtl of demux is
9. signal t : std_logic_vector (3 downto 0);
10. begin
11. t(3) <= s(1) and s(0);
12. t(2) <= s(1) and not s(0);
13. t(1) <= not s(1) and s(0);
14. t(0) <= not s(1) and not s(0);
15. d <= e and t;
end rtl;
Before we look at this example line by line, we need an
introduction to a new declaration, SIGNAL. This declaration is used to
define an internal signal for our design. In the entity block we defined
interfacing or external signals that take information in and return data
out. Internal signals are those used to perform some internal
connections or function between logic entities. A signal declaration
has the syntax:
signal signal_identifier : type;
It is similar to a port signal declaration except for the lack of a
mode indication.
In the demux example, the entity has three array declarations,
two are 4-bits (e and d) and one is 2-bits (s). Within the architecture
block, a local signal is declared as a 4-bit array (t). The values for t are
assigned in descending order directed by the four state combinations
of s(1) and s(0). Notice how each element is accessed using the array

name and an index value. t(3) is assigned the results of anding s(1)
and s(0). This is a single bit manipulation and assignment of one bit
from each array, bits t(3), s(1), and s(0). The last line shows how array
values can be assigned for the entire array at one time. The crucial
requirement is that all arrays in the assignment statement have the
same size. If that is the case, than each element of each array is
acted upon individually. ie:
d(3) <= e(3) and t(3)
etc.
Since vectors can be assigned using to as well as downto, care
must be taken in the assignment. If, in the previous example, d was
declared as d : out std_logic_vector( 0 to 3); than the assignment d <=
e and t; would assign to d(0) the result of e(3) and t(3) which may not
be what you intended.
PROCESS
Statements within architecture blocks, to this point, are
executed concurrently - that is at the same time. Also, there is no way
to synchronize their execution with clocking or any other kind of
signals. To incorporate sequential statement execution and some
manner of synchronization, we need to use a PROCESS block whose
general syntax form is:
process_name : process (sensitivity list)
variable variable_names : variable_type;
begin
statements;
end process;
Process statements are placed in the architecture block of your
design. The process_name and variable declarations are optional.
Process names are handy if your design contains more than one
process. Variable declarations are used to define a variable local to
and used by the process. Variable declarations are added in the
declaration area preceding the body of the process block. In contrast
to a signal, variable declarations define memory locations, identified
by variable identifier names, used to store results of expressions.
Signals, by their nature, cannot be used to perform arithmetic
manipulations such as incrementing or decrementing their value while

variables can be operated on mathematically. The variable
assignment operator is := which is the same one used for assigning
initial literal values. The syntax for a variable assignment is:
variable_identifier := expression;
To evaluate expressions used in a variable declaration or
process block, you must become familiar with the operators used by
VHDL. Many of them are not strangers to anyone who has any kind of
programming experience. In order of their precedence, they are:
o Highest
() - parenthesis
** - exponential
abs - absolute unsigned magnitude numbers
not - inversion
o Next
* - multiplication
/ - division
mod - modulo or quotient from division
rem - remainder result of division
o Next
+ - identity
- - negation
o Next
+ - addition
- - subtraction
& - concatenation
o Next
sll - shift left logical
srl - shift right logical
sla - shift left arithmetic
sra - shift right arithmetic
rol - rotate left
ror - rotate right
o Next
= - equality
/= - not equal
< - less than
> - greater than
<= - less than or equal
>= - greater than or equal

o LOWEST
and - logic and
or - logic or
nand - logic nand
nor - logic nor
xor - logic exclusive or
xnor - logic exclusive nor
CONDITIONAL STATEMENTS
The primary conditional test function is the if..then..else construct
that works the same as it does in any programming language. The
syntax for this function is:
if conditional_test then
statements;
else
statements;
end if;
The statements following then are executed if the condition is
true. The else block is optional and used only if there is an alternate
process required to be done if the conditional result is false. If
statements can be nested using an elsif block. In that case, the syntax
is:
if conditional test then
statements;
elsif conditional test then
statements;
else
statements;
end if;
• if..then..else Short Form, the WHEN statement:
identifier <= expression_true
WHEN condition
ELSE expression_false;
Example:

Y <= A and B WHEN S = '0'
ELSE A or B;
• Full WHEN statement
identifier <= expression1
WHEN condition 1
ELSE expression2 WHEN condition2
ELSE expression3 WHEN condition3
ELSE expressionN WHEN OTHERS;
Identifier is assigned the expression for the WHEN condition
that is true.
Example:
print1 <=
user1 WHEN (en = '1' and sel = '0') ELSE
user2 WHEN (en = '1' and sel = '1') ELSE
user3 WHEN OTHERS;
• CASE Statement
FONT color="#0000FF">CASE test_var IS
WHEN test_val1 => identifier <= expression1;
WHEN OTHERS => identifier <= expression6;
:= may be used instead of <=
Conditional test is done on all values concurrently. Assignment is
made for true WHEN condition.
Example:
TYPE op IS (ADD, SUB, MUL, DIV);
SIGNAL op_code : op;
PROCESS (op_code, A, B)
BEGIN
CASE op_code IS

WHEN ADD => Y := A + B;
WHEN SUB => Y := A - B;
WHEN MUL = > Y := A * B;
WHEN DIV => Y := A * B;
WHEN OTHERS => Y := Y;
END CASE;
END PROCESS;
• WITH Statement
WITH test_variable SELECT
identifier <=
expression1 WHEN test_val1,
expression4 WHEN OTHERS;
Example
WITH SEL SELECT
Y <=
A WHEN "00",
B WHEN "01",
C WHEN "10",
D WHEN "11",
'Z" WHEN OTHERS;
LOOPS
The for loop is used to repeat the execution of a section of code
for a given number of times. The general syntax for a for loop is:
for variable in range loop
statements;
end loop;
The range has the same format as the range used in a
bit_vector assignment except, in a for statement, it also defines the

direction for the value of the variable for each iteration of the loop (to
increments and downto decrements).

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