This is the slides presented to FSE conference.

1. Logical Time @ work: the project
Julien DeAntoni, Frédéric Mallet
I3S/UNS/INRIA
Frédéric Thomas, Gonzague Reydet
Obeo
Jean-Philippe Babau
UBO
and more...
FSE 2010 1

2. Logical Time @ work: the project
Julien DeAntoni, Frédéric Mallet
I3S/UNS/INRIA
Frédéric Thomas, Gonzague Reydet
Obeo
Jean-Philippe Babau
UBO
and more...
FSE 2010 2

3. Logical Time...
• focuses on causal relations between events
• Is independent of the abstraction level
• Is multi-clock (polychronous)
• Provides a partial order between events
After 23 starts of the computer, a disk check is done
The computation duration is 156 processor ticks
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4. Logical Time...
• focuses on causal relations between events
• Is independent of the abstraction level
• Is multi-clock (polychronous)
• Provides a partial order between events
After 23 starts of the computer, a disk check is done
The computation duration is 156 processor ticks
In modern laptop, tick is logical since the
processor speed depend on the battery level
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5. Logical Time...
• focuses on causal relations between events
• Is independent of the abstraction level
• Is multi-clock (polychronous)
• Provides a partial order between events
LOGICAL TIME
Friedemann Mattern
Darmstadt University of Technology
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6. Physical Time...
• Can be seen as a special case of logical time
After 5 secondes, it stops...
≅
After 5 events of the “second” clock, it stops
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7. Logical Time @ work: the project
Julien DeAntoni, Frédéric Mallet
I3S/UNS/INRIA
Frédéric Thomas, Étienne Juliot
Obeo
Jean-Philippe Babau
UBO
and more...
FSE 2010 7

8. Retro-ingénierie de Traces d'analyse de
SIMulation
et d'EXécution de systèmes temps-réel
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9. Context : help the designer
Designer Code Real time
Multi-task
execution
Analysis of the
execution
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10. Context: execution traces
Designer Code Real time
Multi-task
execution
JumpShot , Vampir,
Linux Tool Eclipse Project Exection analysis Temporal execution traces
and reports
OTF, VCD
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11. observations
Designer Model Code Real time
Multi-task
execution
SDL,
AADL ...
Execution Temporal execution
analysis and traces
report
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12. RT-Simex objectives
Designer Models Code Real time
Multi-task
execution
UML MARTE
Eclipse
Execution analysis
Temporal execution
and report AT THE traces
MODEL LEVEL
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13. Processus RT-Simex
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14. Logical Time @ work: the project
Julien DeAntoni, Frédéric Mallet
I3S/UNS/INRIA
Frédéric Thomas, Gonzague Reydet
Obeo
Jean-Philippe Babau
UBO
and more...
FSE 2010 14

15. MARTE TIME MODEL
• SubProfile of the MARTE UML profile
standardized by the OMG (Object
Management Group)
– Reviewed and accepted by the community
– Implemented in Papyrus, magic draw, etc
– Under Implementation in other UML tools
• A Domain Model integrated with eclipse and
usable with Domain Specific Language
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16. MARTE TIME MODEL
• The main concept is the Clock.
– It is a way to specify a, possibly infinite,
ordered set of instants
– It can be logical or chronometric, discrete or
dense
– Its type is a ClockType
itsResolution = 1
= TAI
= discrete
tick
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17. MARTE TIME MODEL
1..*
itsResolution = 1
= TAI
Simplified view of the MARTE Time meta-Model
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18. MARTE TIME MODEL
• Sketchy example of its use
Producer Consumer
c1
User model
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19. MARTE TIME MODEL
• Sketchy example of its use
Producer Consumer
c1
User model
sendEvent receiveEvent
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20. MARTE TIME MODEL
• Sketchy example of its use
Producer Consumer
c1
User model
sendEvent receiveEvent
on on
c1.sendEvent: LogicalClock c1.receiveEvent: LogicalClock
MARTE model
LogicalClock : ClockType
IsLogical : True
Nature : discrete The ordered set of sendEvent
is bijective with the ordered set
of instants of c1.sendEvent
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21. CCSL
• Clock Constraint Specification Language
– Firstly introduced in the MARTE TIME
profile
– Declarative model-based language
integrated with Eclipse
– Formal semantics (both denotational
and operational)
– Tooled (TimeSquare)
→ Explicitly represents / specifies relations
between clocks
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22. CCSL (Clock Constraint Specification Language)
– Relations: dependencies between clocks
• Coincidence → =
• Exclusion → #
• Precedence → <
• Alternance → ~
– Expressions: a mean to create new clocks
from others
• Delay → delayedFor X on aClock
• Filtering → aClock filteredBy aBinaryWord
• Union → aClock union anotherClock
• Intersection → aClock inter anotherClock
• Periodicity → periodicOn aClock period X offset Y
• …
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23. CCSL (Clock Constraint Specification Language)
– Relations: dependencies between clocks
• Coincidence → =
• Exclusion → #
• Precedence → <
• Alternance → ~
– Expressions: a mean to create new clocks
from others
• Delay → delayedFor X on aClock
• Filtering → aClock filteredBy aBinaryWord
• Union → aClock union anotherClock
• Intersection → aClock inter anotherClock
• Periodicity → periodicOn aClock period X offset Y
– Libraries: user-defined relations and
expressions
• … 23
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24. CCSL
• Sketchy example of its use
Producer Consumer
c1
User model
sendEvent receiveEvent
on on
c1.sendEvent: LogicalClock c1.receiveEvent: LogicalClock
MARTE model
LogicalClock : ClockType
IsLogical : True
Nature : discrete The ordered set of sendEvent
is bijective with the ordered set
of instants of c1.sendEvent
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25. CCSL
• Sketchy example of its use
Producer Consumer
c1
User model
sendEvent receiveEvent
on on
c1.sendEvent: LogicalClock c1.receiveEvent: LogicalClock
MARTE model
LogicalClock : ClockType
IsLogical : True
left
Nature : discrete right
R1 : Precedes
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26. Graphical formal annotation over a UML model
for RT-Simex...
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27. Simulate and animate the UML/MARTE model
in TimeSquare
(http://www-sop.inria.fr/aoste/dev/time_square/)
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28. Processus RT-Simex
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29. Processus RT-Simex
CCSL
specification
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30. Processus RT-Simex
CCSL
specification
For a specific platform, this is a total order...
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31. Processus RT-Simex
CCSL
specification
For a specific platform, this is a total order...
For two communicating platforms,
the traces are multi-clocks...
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32. Processus RT-Simex
CCSL
specification
If simulated it replays the execution...
CCSL
specification
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33. Processus RT-Simex
CCSL
specification
If simulated it replays the execution...
So you can have a timing diagram,
animate the model and so on...
CCSL
specification
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34. A specification and the actual execution
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35. Processus RT-Simex
CCSL
specification
CCSL
specification
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36. Processus RT-Simex
CCSL
assertions
CCSL
specification
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37. Processus RT-Simex
CCSL
assertions You can simulation both together to
CCSL see if a violation occurs
specification
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38. Processus RT-Simex
You can simulation both together to
see if a violation occurs
CCSL Violation of “Clk3b isSubClockOf clk3”
assertions
CCSL
specification
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39. Conclusion
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